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M
Device PIC16C63A PIC16C73B PIC16C65B PIC16C74B Pins 28 28 40 40
PIC16C63A/65B/73B/74B
A/D NO YES NO YES PSP NO NO YES YES
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
28/40-Pin 8-Bit CMOS Microcontrollers
Pin Diagram
PDIP, Windowed CERDIP
Microcontroller Core Features:
* High-performance RISC CPU * Only 35 single word instructions to learn * All single cycle instructions except for program branches which are two cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * 4K x 14 words of Program Memory, 192 x 8 bytes of Data Memory (RAM) * Interrupt capability (up to 12 internal/external interrupt sources) * Eight level deep hardware stack * Direct, indirect, and relative addressing modes * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Selectable oscillator options * Low-power, high-speed CMOS EPROM technology * Fully static design * In-Circuit Serial ProgrammingTM (ICSP) * Wide operating voltage range: 2.5V to 5.5V * High Sink/Source Current 25/25 mA * Commercial, Industrial and Extended temperature ranges * Low-power consumption: - < 2 mA @ 5V, 4 MHz - 22.5 A typical @ 3V, 32 kHz - < 1 A typical standby current
Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Two Capture, Compare, PWM modules * Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM maximum resolution is 10-bit * 8-bit multi-channel Analog-to-Digital converter * Synchronous Serial Port (SSP) with Enhanced SPITM and I2CTM * Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) * Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls * Brown-out detection circuitry for Brown-out Reset (BOR)
(c) 1998 Microchip Technology Inc.
PIC16C74B
DS30605A-page 1
PIC16C63A/65B/73B/74B
Pin Diagrams
SDIP, SOIC, SSOP, Windowed CERDIP SDIP, SOIC, SSOP, Windowed CERDIP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL
*1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL
*1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
PIC16C73B
PIC16C63A
PDIP, Windowed CERDIP
MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS RE0/RD RE1/WR RE2/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
MQFP TQFP
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9 10 11
PIC16C65B
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS RE1/WR RE0/RD RA5/SS RA4/T0CKI
PIC16C65B
PLCC
6 5 4 3 2 1 44 43 42 41 40
RA3 RA2 RA1 RA0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC
RA4/T0CKI RA5/SS RE0/RD RE1/WR RE2/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC
7 8 9 10 11 12 13 14 15 16 17
PIC16C65B
39 38 37 36 35 34 33 32 31 30 29
RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT
RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC
18 19 20 21 22 23 24 25 26 27 28
DS30605A-page 2
NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0 RA1 RA2 RA3
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Pin Diagrams (Cont.'d)
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC 44 43 42 41 40 39 38 37 36 35 34 RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC
PLCC
MQFP TQFP
6 5 4 3 2 1 44 43 42 41 40
RA4/T0CKI RA5/SS/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC
7 8 9 10 11 12 13 14 15 16 17
PIC16C74B
39 38 37 36 35 34 33 32 31 30 29
RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9 10 11
PIC16C74B
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/SS/AN4 RA4/T0CKI
RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC
18 19 20 21 22 23 24 25 26 27 28
Key Features PICmicroTM Mid-Range Reference Manual (DS33023) Operating Frequency Resets (and Delays) Program Memory (14-bit words) Data Memory (bytes) Interrupts I/O Ports Timers Capture/Compare/PWM modules Serial Communications Parallel Communications 8-bit Analog-to-Digital Module Instruction Set
PIC16C63A DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 10 Ports A,B,C 3 2 SSP, USART -- -- 35 Instructions
PIC16C65B DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 11 3 2 SSP, USART PSP -- 35 Instructions
NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF
PIC16C73B DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 11 3 2 SSP, USART -- 35 Instructions
PIC16C74B DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 12 Ports A,B,C,D,E 3 2 SSP, USART PSP 35 Instructions
Ports A,B,C,D,E Ports A,B,C
5 input channels 8 input channels
(c) 1998 Microchip Technology Inc.
DS30605A-page 3
PIC16C63A/65B/73B/74B
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization................................................................................................................................................................. 11 3.0 I/O Ports ..................................................................................................................................................................................... 25 4.0 Timer0 Module ........................................................................................................................................................................... 37 5.0 Timer1 Module ........................................................................................................................................................................... 39 6.0 Timer2 Module ........................................................................................................................................................................... 43 7.0 Capture/Compare/PWM (CCP) Module(s)................................................................................................................................. 45 8.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 51 9.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) .................................................................................... 61 10.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 75 11.0 Special Features of the CPU...................................................................................................................................................... 81 12.0 Instruction Set Summary............................................................................................................................................................ 95 13.0 Development Support ................................................................................................................................................................ 97 14.0 Electrical Characteristics.......................................................................................................................................................... 101 15.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 123 16.0 Packaging Information ............................................................................................................................................................. 125 Appendix A: Revision History ........................................................................................................................................................... 137 Appendix B: Device Differences ....................................................................................................................................................... 137 Appendix C: Conversion Considerations .......................................................................................................................................... 137 Appendix D: Migration from Baseline to Midrange Devices.............................................................................................................. 138 Appendix E: Bit/Register Cross-Reference List ................................................................................................................................ 139 Index .................................................................................................................................................................................................. 141 On-Line Support................................................................................................................................................................................. 147 Reader Response .............................................................................................................................................................................. 148 PIC16C63A/65B/73B/74B Product Identification System .................................................................................................................. 149
To Our Valued Customers
Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our worldwide web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number, found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's worldwide web site at http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: * Fill out and mail in the reader response form in the back of this data sheet, or * E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document.
DS30605A-page 4
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
1.0 DEVICE OVERVIEW
This document contains device-specific information. Additional information may be found in the PICmicroTM Mid-Range Reference Manual (DS33023) which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are four devices (PIC16C63A, PIC16C65B, PIC16C73B, PIC16C74B) covered by this data sheet. These devices come in 28- and 40-pin packages. The 28-pin devices do not have a Parallel Slave Port implemented. The PIC16C6X devices do not have the A/D module implemented. The following two figures are device block diagrams sorted by pin number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are listed in Table 1-1 and Table 1-2 respectively.
FIGURE 1-1:
PIC16C63A/PIC16C73B BLOCK DIAGRAM
13 Program Counter EPROM 4K x 14 Program Memory 8 Level Stack (13-bit) RAM 192 x 8 File Registers RAM Addr(1) 9 PORTB Data Bus 8 PORTA RA0/AN0(2) RA1/AN1(2) RA2/AN2(2) RA3/AN3/VREF(2) RA4/T0CKI RA5/SS/AN4(2)
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8 W reg ALU PORTC
MUX
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
MCLR
VDD, VSS
Timer0
Timer1
Timer2
A/D(2)
CCP1
CCP2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register. 2: The A/D module is not available on the PIC16C63A.
(c) 1998 Microchip Technology Inc.
DS30605A-page 5
PIC16C63A/65B/73B/74B
FIGURE 1-2: PIC16C65B/PIC16C74B BLOCK DIAGRAM
13 EPROM 4K x 14 Program Memory Program Bus 14 Instruction reg Direct Addr 7 8 Level Stack (13-bit) Program Counter Data Bus 8 PORTA RA0/AN0(2) RA1/AN1(2) RA2/AN2(2) RA3/AN3/VREF(2) RA4/T0CKI RA5/SS/AN4(2) PORTB
RAM 192 x 8 File Registers RAM Addr (1) 9
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD W reg RD7/PSP7:RD0/PSP0
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
Parallel Slave Port MCLR VDD, VSS
PORTE RE0/RD/AN5(2) RE1/WR/AN6(2)
Timer0
Timer1
Timer2
A/D(2)
RE2/CS/AN7(2)
CCP1
CCP2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register. 2: The A/D module is not available on the PIC16C65B.
DS30605A-page 6
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 1-1:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16C63A/PIC16C73B PINOUT DESCRIPTION
DIP Pin# 9 10 SOIC Pin# 9 10 I/O/P Type I O Buffer Type Description
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0 RA1 can also be analog input1 RA2 can also be analog input2 RA3 can also be analog input3 or analog reference voltage RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0 can also be the external interrupt pin.
MCLR/VPP
1
1
I/P
ST
RA0/AN0(4) RA1/AN1(4) RA2/AN2(4) RA3/AN3/VREF(4) RA4/T0CKI RA5/SS/AN4(4)
2 3 4 5 6 7
2 3 4 5 6 7
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT VSS VDD Legend: I = input Note 1: 2: 3: 4:
21 22 23 24 25 26 27 28 11 12 13 14 15 16 17 18 8, 19 20
21 22 23 24 25 26 27 28 11 12 13 14 15 16 17 18 8, 19 20
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) ST ST ST ST ST ST ST ST -- --
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. The A/D module is not available on the PIC16C63A.
(c) 1998 Microchip Technology Inc.
DS30605A-page 7
PIC16C63A/65B/73B/74B
TABLE 1-2:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16C65B/PIC16C74B PINOUT DESCRIPTION
DIP Pin# 13 14 PLCC Pin# 14 15 QFP Pin# 30 31 I/O/P Type I O Buffer Type ST/CMOS(4) -- Description Oscillator crystal input/external clock source input. Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port.
MCLR/VPP
1
2
18
I/P
ST
RA0/AN0(5) RA1/AN1(5) RA2/AN2(5) RA3/AN3/VREF(5) RA4/T0CKI RA5/SS/AN4(5)
2 3 4 5 6 7
3 4 5 6 7 8
19 20 21 22 23 24
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RA0 can also be analog input0 RA1 can also be analog input1 RA2 can also be analog input2 RA3 can also be analog input3 or analog reference voltage RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 Legend: I = input Note 1: 2: 3: 4: 5:
33 34 35 36 37 38 39
36 37 38 39 41 42 43
8 9 10 11 14 15 16
I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2)
RB0 can also be the external interrupt pin.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock.
40 44 17 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. The A/D module is not available on the PIC16C65B.
DS30605A-page 8
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 1-2:
Pin Name
PIC16C65B/PIC16C74B PINOUT DESCRIPTION (Cont.'d)
DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
15 16 17 18 23 24 25 26
16 18 19 20 25 26 27 29
32 35 36 37 42 43 44 1
I/O I/O I/O I/O I/O I/O I/O I/O
ST ST ST ST ST ST ST ST
RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.
RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RE0/RD/AN5(5) RE1/WR/AN6(5) RE2/CS/AN7(5) VSS VDD NC Legend: I = input Note 1: 2: 3: 4: 5:
19 20 21 22 27 28 29 30 8 9 10 12,31 11,32 --
21 22 23 24 30 31 32 33 9 10 11 13,34 12,35 1,17,28, 40
38 39 40 41 2 3 4 5 25 26 27 6,29 7,28 12,13, 33,34
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P
ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) PORTE is a bi-directional I/O port. ST/TTL(3) ST/TTL(3) ST/TTL(3) -- -- -- RE0 can also be read control for the parallel slave port, or analog input5. RE1 can also be write control for the parallel slave port, or analog input6. RE2 can also be select control for the parallel slave port, or analog input7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected.
O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. The A/D module is not available on the PIC16C65B.
(c) 1998 Microchip Technology Inc.
DS30605A-page 9
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 10
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.0 MEMORY ORGANIZATION
2.2 Data Memory Organization
There are two memory blocks in each of these PICmicro microcontrollers. Each block (Program Memory and Data Memory) has its own bus so that concurrent access can occur. Additional information on device memory may be found in the PICmicroTM Mid-Range Reference Manual (DS33023). The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1(1) = 00 = 01 = 10 = 11 RP0 (STATUS<6:5>)
2.1
Program Memory Organization
The PIC16C63A/65B/73B/74B microcontrollers have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Each device has 4K x 14 words of program memory. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.
Bank0 Bank1 Bank2 (not implemented) Bank3 (not implemented)
Note 1: Maintain this bit clear to ensure upward compatibility with future products.
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK
PC<12:0>
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some "high use" special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 GENERAL PURPOSE REGISTER FILE
CALL, RETURN RETFIE, RETLW
13
The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 2.5).
Stack Level 1
Stack Level 8 Reset Vector
0000h
User Memory Space
Interrupt Vector On-chip Program Memory (Page 0)
0004h 0005h 07FFh
On-chip Program Memory (Page 1)
0800h
0FFFh 1000h
1FFFh
(c) 1998 Microchip Technology Inc.
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PIC16C63A/65B/73B/74B
FIGURE 2-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE(2) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES(3) ADCON0(3)
REGISTER FILE MAP
File Address INDF(1) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(2) TRISE(2) PCLATH INTCON PIE1 PIE2 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is give in Table 2-1. The special function registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section.
PR2 SSPADD SSPSTAT
TXSTA SPBRG
ADCON1(3)
General Purpose Register
General Purpose Register
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These registers are not implemented on the PIC16C63A/73B, read as '0'. 3: These registers are not implemented on the PIC16C63A/65B, read as '0'.
DS30605A-page 12
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PIC16C63A/65B/73B/74B
TABLE 2-1
Addr Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets (5)
Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF(1) TMR0 PCL(1) STATUS(1) FSR(1) PORTA(7) PORTB(8) PORTC(8) PORTD(3,8) PORTE(3,8) PCLATH(1,2) INTCON(1) PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES(4) ADCON0(4) Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP(6) RP1(6) RP0 TO PD Z DC C 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 rr01 1xxx rr0q quuu xxxx xxxx uuuu uuuu --0x 0000 --0u 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu RE2 RE1 RE0 ---- -xxx ---- -uuu ---0 0000 ---0 0000 0000 000x 0000 000u 0000 0000 0000 0000 ---- ---0 ---- ---0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1CS TMR1ON --00 0000 --uu uuuu 0000 0000 0000 0000 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 -- CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D --00 0000 --00 0000 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu CHS2 CHS1 CHS0 GO/DONE -- ADON 0000 00-0 0000 00-0
Indirect data memory address pointer -- -- PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- -- GIE PSPIF(3) -- -- -- PEIE ADIF(4) -- -- -- T0IE RCIF -- -- --
Write Buffer for the upper 5 bits of the Program Counter INTE TXIF - RBIE SSPIF -- T0IF CCP1IF -- INTF TMR2IF -- RBIF TMR1IF CCP2IF
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Timer2 module's register -- TOUTPS3 TOUTPS2
Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) -- -- CCP2X CCP2Y
A/D Result Register ADCS1 ADCS0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as '0'. 4: A/D not implemented on the PIC16C63A/65B, maintain as '0'. 5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 6: The IRP and RP1 bits are reserved. Always maintain these bits clear. 7: On any device reset, these pins are configured as inputs. 8: This is the value that will be in the port output latch.
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TABLE 2-1
Addr Name
SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets (5)
Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh PR2 SSPADD SSPSTAT -- -- -- TXSTA SPBRG -- -- -- -- -- ADCON1(4) INDF(1) OPTION_REG PCL(1) STATUS(1) FSR
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte IRP(6) RP1(6) RP0 TO PD Z DC C
rr01 1xxx rr0q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
Indirect data memory address pointer -- -- PORTA Data Direction Register
TRISA TRISB TRISC TRISD(3) TRISE(3) PCLATH(1,2) INTCON(1) PIE1 PIE2 PCON -- -- --
PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF -- GIE PSPIE(3) -- -- Unimplemented Unimplemented Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF OBF -- PEIE ADIE(4) -- -- IBOV -- T0IE RCIE -- -- PSPMODE -- PORTE Data Direction Bits
0000 -111 0000 -111 ---0 0000 ---0 0000 0000 000x 0000 000u 0000 0000 0000 0000 ---- ---0 ---- ---0 ---- --qq ---- --uu -- -- -- -- -- --
Write Buffer for the upper 5 bits of the Program Counter INTE TXIE -- -- RBIE SSPIE -- -- T0IF CCP1IE -- -- INTF TMR2IE -- POR RBIF TMR1IE CCP2IE BOR
1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- -- --
Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D
0000 -010 0000 -010 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- ---- -000
Baud Rate Generator Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0
---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as '0'. 4: A/D not implemented on the PIC16C63A/65B, maintain as '0'. 5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 6: The IRP and RP1 bits are reserved. Always maintain these bits clear. 7: On any device reset, these pins are configured as inputs. 8: This is the value that will be in the port output latch.
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PIC16C63A/65B/73B/74B
2.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 2-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." Note 1: These devices do not use bits IRP and RP1 (STATUS<7:6>). Maintain these bits clear to ensure upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 2-3:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear 0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) - not implemented, maintain clear 10 = Bank 2 (100h - 17Fh) - not implemented, maintain clear 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
DS30605A-page 15
PIC16C63A/65B/73B/74B
2.2.2.2 OPTION_REG REGISTER Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 2-4:
R/W-1 RBPU bit7
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
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PIC16C63A/65B/73B/74B
2.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
FIGURE 2-5:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
R/W-0 PEIE
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt IINTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
DS30605A-page 17
PIC16C63A/65B/73B/74B
2.2.2.4 PIE1 REGISTER Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. This register contains the individual enable bits for the peripheral interrupts.
FIGURE 2-6:
R/W-0 PSPIE(1) bit7
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit0
R/W-0 ADIE(2)
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE(2): A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these devices. Always maintain this bit clear. 2: PIC16C63A/65B devices do not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear.
DS30605A-page 18
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PIC16C63A/65B/73B/74B
2.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 2-7:
R/W-0 PSPIF(1) bit7
PIR1 REGISTER (ADDRESS 0Ch)
R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit0
R/W-0 ADIF(2)
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF(2): A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these devices. Always maintain this bit clear. 2: PIC16C63A/65B devices do not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear.
(c) 1998 Microchip Technology Inc.
DS30605A-page 19
PIC16C63A/65B/73B/74B
2.2.2.6 PIE2 REGISTER This register contains the individual enable bit for the CCP2 peripheral interrupt.
FIGURE 2-8:
U-0 -- bit7
PIE2 REGISTER (ADDRESS 8Dh)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CCP2IE bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt
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2.2.2.7 PIR2 REGISTER
.
This register contains the CCP2 interrupt flag bit.
Note:
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 2-9:
U-0 -- bit7
PIR2 REGISTER (ADDRESS 0Dh)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CCP2IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused
(c) 1998 Microchip Technology Inc.
DS30605A-page 21
PIC16C63A/65B/73B/74B
2.2.2.8 PCON REGISTER Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. If the BODEN configuration bit is set, BOR is '1' on Power-on Reset. If the BODEN configuration bit is clear, BOR is unknown on Power-on Reset. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the BODEN configuration bit is clear). BOR must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred.
FIGURE 2-10: PCON REGISTER (ADDRESS 8Eh)
U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-q BOR bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 0:
DS30605A-page 22
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PIC16C63A/65B/73B/74B
2.3 PCL and PCLATH 2.4 Program Memory Paging
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. 2.3.1 STACK The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper bit of the address is provided by PCLATH<3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bit is programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the return instructions (which POPs the address from the stack).
The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Mid-Range devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
(c) 1998 Microchip Technology Inc.
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PIC16C63A/65B/73B/74B
2.5 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
EXAMPLE 2-2:
HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
EXAMPLE 2-1:
* * * *
INDIRECT ADDRESSING
Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 06) * A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).
NEXT
movlw movwf clrf incf btfss goto :
CONTINUE
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-11. However, IRP is not used in the PIC16C63A/65B/73B/74B.
FIGURE 2-11: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0 6 from opcode 0 IRP
Indirect Addressing
7 FSR register 0
(2)
bank select location select 00 00h 01 80h 10 100h 11 180h
(2)
bank select location select
Data Memory(1)
not used (3) (3)
7Fh
FFh
17Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: For register file map detail see Figure 2-2. 2: Maintain RP1 and IRP as clear for upward compatibility with future products. 3: Not implemented.
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PIC16C63A/65B/73B/74B
3.0 I/O PORTS
FIGURE 3-1:
Data bus WR Port
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
Q VDD
D
CK
Q
P
3.1
PORTA and the TRISA Register
Data Latch D WR TRIS Q N I/O pin(1)
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin. Note: On a Power-on Reset, these pins are configured as inputs and read as '0'.
CK
Q
TRIS Latch
VSS Analog input mode (73B/74B only) TTL input buffer D
RD TRIS Q
Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read. This value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. On PIC16C73B/74B devices, other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
EN RD PORT
To A/D Converter (73B/74B only) Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 3-2:
Data bus WR PORT
BLOCK DIAGRAM OF RA4/T0CKI PIN
D Q Q
CK
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
N Data Latch
D Q Q
I/O pin(1)
VSS Schmitt Trigger input buffer
WR TRIS
CK
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6> are always read as '0'.
TRIS Latch
STATUS, RP0 PORTA
RD TRIS
Q D EN EN
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISA
RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only.
(c) 1998 Microchip Technology Inc.
DS30605A-page 25
PIC16C63A/65B/73B/74B
TABLE 3-1:
Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 Buffer TTL TTL TTL TTL ST Function Input/output or analog input(1) Input/output or analog input(1) Input/output or analog input(1) Input/output or analog input(1) or VREF(1) Input/output or external clock input for Timer0 Output is open drain type
bit5 TTL Input/output or slave select input for synchronous serial port or analog input(1) Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: On PIC16C73B/74B devices only.
TABLE 3-2:
Address Name 05h 85h 9Fh PORTA TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 Bit 6 -- -- -- -- -- -- Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR --0x 0000 --11 1111 PCFG2 PCFG1 PCFG0 ---- -000 Value on all other resets --0u 0000 --11 1111 ---- -000
PORTA Data Direction Register -- -- --
ADCON1(1)
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: On PIC16C73B/74B devices only.
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PIC16C63A/65B/73B/74B
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
STATUS, RP0 PORTB
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-4:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
FIGURE 3-3:
RBPU(2)
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
RBPU(2)
Data bus WR Port
Data bus WR Port
WR TRIS TTL Input Buffer
CK
TTL Input Buffer
ST Buffer
WR TRIS
CK
RD TRIS Q RD TRIS Q RD Port D EN From other RB7:RB4 pins RB0/INT Schmitt Trigger Buffer RD Port RB7:RB6 in serial programming mode Set RBIF RD Port
Latch D EN Q1
Q
D RD Port EN Q3
Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
(c) 1998 Microchip Technology Inc.
DS30605A-page 27
PIC16C63A/65B/73B/74B
TABLE 3-3:
Name RB0/INT
PORTB FUNCTIONS
Bit# bit0 Buffer TTL/ST(1) Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4:
Address 06h 86h 81h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on POR, BOR xxxx xxxx 1111 1111 PSA PS2 PS1 PS0 1111 1111 Value on all other resets uuuu uuuu 1111 1111 1111 1111
Name PORTB TRISB OPTION_ REG
PORTB Data Direction Register RBPU INTEDG T0CS T0SE
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30605A-page 28
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PIC16C63A/65B/73B/74B
3.3 PORTC and the TRISC Register FIGURE 3-5:
PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin. PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORT/PERIPHERAL Select(2) Peripheral Data Out Data bus WR PORT
D CK Q
0 1
Q
VDD P
Data Latch WR TRIS
D CK Q Q
I/O pin(1) N VSS
TRIS Latch Schmitt Trigger
Q D EN
RD TRIS Peripheral OE(3) RD PORT Peripheral input
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTC
; ; ; ; ; ; ; ; ; ; ; Select Bank 0 Initialize PORTC by clearing output data latches Select Bank 1 Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs
STATUS, RP0 PORTC
BSF MOVLW
STATUS, RP0 0xCF
Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active.
MOVWF
TRISC
(c) 1998 Microchip Technology Inc.
DS30605A-page 29
PIC16C63A/65B/73B/74B
TABLE 3-5:
Name RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7
PORTC FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input Input/output port pin or Timer1 oscillator input Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output Input/output port pin Input/output port pin
Legend: ST = Schmitt Trigger input
TABLE 3-6:
Address Name 07h 87h PORTC TRISC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on POR, BOR xxxx xxxx 1111 1111 Value on all other resets uuuu uuuu 1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged.
DS30605A-page 30
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.4 PORTD and TRISD Registers
to the This section is applicable PIC16C65B/PIC16C74B devices only.
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
FIGURE 3-6:
Data bus WR PORT
PORTD BLOCK DIAGRAM (IN I/O PORT MODE)
D Q
I/O pin(1)
CK
Data Latch
D Q
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
RD TRIS
Q D EN EN
RD PORT Note 1: I/O pins have protection diodes to VDD and VSS.
(c) 1998 Microchip Technology Inc.
DS30605A-page 31
PIC16C63A/65B/73B/74B
TABLE 3-7:
Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6
PORTD FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) Function Input/output port pin or parallel slave port bit0 Input/output port pin or parallel slave port bit1 Input/output port pin or parallel slave port bit2 Input/output port pin or parallel slave port bit3 Input/output port pin or parallel slave port bit4 Input/output port pin or parallel slave port bit5 Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7 RD7/PSP7 bit7 ST/TTL(1) Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
TABLE 3-8:
Address Name 08h 88h 89h PORTD TRISD TRISE
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7 Bit 6 RD7 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on POR, BOR xxxx xxxx 1111 1111 -- PORTE Data Direction Bits 0000 -111 Value on all other resets uuuu uuuu 1111 1111 0000 -111
PORTD Data Direction Register IBF OBF IBOV PSPMODE
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
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PIC16C63A/65B/73B/74B
3.5 PORTE and TRISE Register
Note: This section is applicable to the PIC16C65B/PIC16C74B devices only. The A/D multiplexed functions are available on the PIC16C74B only. PORTE has three pins RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). For the PIC16C74B ensure ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. Figure 3-8 shows the TRISE register, which also controls the parallel slave port operation. PORTE pins for the PIC16C74B only are multiplexed with analog inputs. When selected as an analog input, these pins will read as '0's. TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs.
RD PORT Note 1: I/O pins have protection diodes to VDD and VSS.
On a Power-on Reset these pins are configured as analog inputs.
FIGURE 3-7:
Data bus WR PORT
PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
D Q
I/O pin(1)
CK
Data Latch
D Q
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
RD TRIS
Q D EN EN
FIGURE 3-8:
R-0 IBF bit7
TRISE REGISTER (ADDRESS 89h)
R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 TRISE2 R/W-1 TRISE1 R/W-1 TRISE0 bit0
R-0 OBF
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel slave port mode 0 = General purpose I/O mode Unimplemented: Read as '0' TRISE2: RE2 Direction Control bit 1 = Input 0 = Output TRISE1: RE2 Direction Control bit 1 = Input 0 = Output TRISE0: RE2 Direction Control bit 1 = Input 0 = Output
bit 6:
bit 5:
bit 4:
bit 3: bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
DS30605A-page 33
PIC16C63A/65B/73B/74B
TABLE 3-9:
Name RE0/RD/AN5(2)
PORTE FUNCTIONS
Bit# bit0 Buffer Type ST/TTL(1) Function Input/output port pin or read control input in parallel slave port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected) Input/output port pin or write control input in parallel slave port mode or analog input: WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected)
RE1/WR/AN6(2)
bit1
ST/TTL(1)
Input/output port pin or chip select control input in parallel slave port mode or analog input: CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode. 2: A/D Converter module multiplexing is implemented on the PIC16C74B only.
RE2/CS/AN7(2)
bit2
ST/TTL(1)
TABLE 3-10:
Addr 09h 89h 9Fh Name PORTE TRISE
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7 Bit 6 -- IBF -- -- OBF -- Bit 5 -- IBOV -- Bit 4 -- PSPMODE -- Bit 3 -- -- -- Bit 2 RE2 Bit 1 RE1 Bit 0 RE0 Value on POR, BOR ---- -xxx 0000 -111 ---- -000 Value on all other resets ---- -uuu 0000 -111 ---- -000
PORTE Data Direction Bits PCFG2 PCFG1 PCFG0
ADCON1(1)
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE. Note 1: A/D Converter module multiplexing is implemented on the PIC16C74B only.
DS30605A-page 34
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PIC16C63A/65B/73B/74B
3.6 Parallel Slave Port FIGURE 3-9:
The Parallel Slave Port is implemented on the 40-pin devices only (PIC16C65B and PIC16C74B). PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode it is asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR. It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). For the PIC16C74B, the A/D port configuration bits PCFG2:PCFG0 (ADCON1<2:0>) must be set, which will configure pins RE2:RE0 as digital I/O. A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low.
Data bus
D Q
PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
WR PORT
CK
RDx pin TTL
Q
D EN EN
RD PORT One bit of PORTD
Set interrupt flag PSPIF (PIR1<7>)
Read
TTL
RD CS WR
Chip Select
TTL
Write
TTL
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 3-10: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
(c) 1998 Microchip Technology Inc.
DS30605A-page 35
PIC16C63A/65B/73B/74B
FIGURE 3-11: PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
TABLE 3-11:
Add. Name 08h 09h 89h 0Ch 8Ch 9Fh PORTD PORTE TRISE PIR1 PIE1 ADCON1(1)
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx RE2 RE1 RE0 ---- -xxx 0000 -111 0000 0000 0000 0000 ---- -000 Value on all other resets uuuu uuuu ---- -uuu 0000 -111 0000 0000 0000 0000 ---- -000
Port data latch when written: Port pins when read -- IBF PSPIF PSPIE -- -- OBF ADIF(1) ADIE(1) -- -- -- -- -- SSPIF SSPIE --
IBOV PSPMODE RCIF RCIE -- TXIF TXIE --
PORTE Data Direction Bits CCP1IF CCP1IE PCFG2 TMR2IF TMR2IE PCFG1 TMR1IF TMR1IE PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: On PIC16C74B only.
DS30605A-page 36
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PIC16C63A/65B/73B/74B
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable Internal or external clock select Edge select for external clock 8-bit software programmable prescaler Interrupt on overflow from FFh to 00h Additional information on external clock requirements is available in the PICMicroTM Mid-Range Reference Manual, (DS33023).
4.2
Prescaler
Figure 4-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available, which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer and vice-versa. The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
4.1
Timer0 Operation
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed below. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). There is a delay in the actual incrementing of Timer0 after synchronization.
FIGURE 4-1:
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler T0SE 3 PS2, PS1, PS0 T0CS PSA Set interrupt flag bit T0IF on overflow PSout Sync with Internal clocks (2 cycle delay) TMR0 PSout 8
RA4/T0CKI pin
0
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
(c) 1998 Microchip Technology Inc.
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PIC16C63A/65B/73B/74B
4.2.1 SWITCHING PRESCALER ASSIGNMENT
4.3
Timer0 Interrupt
The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicroTM Mid-Range Reference Manual, (DS33023). must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 4-2:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1:
Address 01h 0Bh, 8Bh 81h 85h
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 --11 1111 Value on all other resets uuuu uuuu 0000 000u 1111 1111 --11 1111
Name TMR0 INTCON OPTION_REG TRISA
Timer0 module's register GIE PEIE T0IE T0CS
RBPU INTEDG -- --
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
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5.0 TIMER1 MODULE
5.1 Timer1 Operation
The Timer1 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L) * Readable and writable (Both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * Reset from CCP module trigger Timer1 has a control register, shown in Figure 5-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Figure 5-2 is a simplified block diagram of the Timer1 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023). Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer1 also has an internal "reset input". This reset can be generated by the CCP module (Section 7.0).
FIGURE 5-1:
U-0 -- bit7
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON
bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1
bit 2:
bit 0:
(c) 1998 Microchip Technology Inc.
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PIC16C63A/65B/73B/74B
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
Set flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0 1 TMR1ON on/off T1SYNC
Synchronized clock input
T1OSC RC0/T1OSO/T1CKI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input Synchronize det
RC1/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
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5.2 Timer1 Oscillator 5.3 Timer1 Interrupt
A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4
Resetting Timer1 using a CCP Trigger Output
TABLE 5-1:
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Freq 32 kHz 100 kHz 200 kHz C1 33 pF 15 pF 15 pF C2 33 pF 15 pF 15 pF
If the CCP module is configured in compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
Osc Type LP
These values are for design guidance only.
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.
Crystals Tested: 32.768 kHz Epson C-001R32.768K-A 20 PPM 100 kHz Epson C-2 100.00 KC-P 20 PPM 200 kHz STD XTL 200.000 kHz 20 PPM Note 1: Higher capacitance increases the stability of the oscillator but also increases the startup time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
TABLE 5-2:
Address Name 0Bh,8Bh 0Ch 8Ch 0Eh 0Fh 10h
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 GIE
(1) (1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE
(1) (1)
Bit 4 INTE
(1) (1)
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF CCP1IF CCP1IE
Bit 1 INTF TMR2IF TMR2IE
Bit 0 RBIF TMR1IF TMR1IE
Value on POR, BOR
Value on all other resets
INTCON PIR1 PIE1 TMR1L TMR1H T1CON
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: These bits are reserved, maintain as '0'.
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NOTES:
DS30605A-page 42
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6.0
* * * * * * *
TIMER2 MODULE
6.1
Timer2 Operation
The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (Both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift
Timer2 can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR2 register * a write to the T2CON register * any device reset (Power-on Reset, MCLR reset, Watchdog Timer reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written.
Timer2 has a control register, shown in Figure 6-1. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 6-2 is a simplified block diagram of the Timer2 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
FIGURE 6-1:
U-0 -- bit7
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
(c) 1998 Microchip Technology Inc.
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6.2 Timer2 Interrupt FIGURE 6-2:
Sets flag bit TMR2IF
TIMER2 BLOCK DIAGRAM
The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset.
TMR2 output (1) Reset Prescaler 1:1, 1:4, 1:16 2
TMR2 reg Comparator
FOSC/4
6.3
Output of TMR2
Postscaler 1:1 to 1:16 4
EQ
The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate shift clock.
PR2 reg
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
TABLE 6-1:
Address 0Bh,8Bh 0Ch 8Ch 11h 12h 92h Name INTCON PIR1 PIE1 TMR2 T2CON PR2
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7 GIE
(1) (1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE
(1) (1)
Bit 4 INTE
(1) (1)
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF CCP1IF CCP1IE
Bit 1 INTF TMR2IF TMR2IE
Bit 0 RBIF TMR1IF TMR1IE
Value on: POR, BOR
Value on all other resets
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111
Timer2 Period Register
Legend: Note 1:
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. These bits are reserved, maintain as '0'.
DS30605A-page 44
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7.0 CAPTURE/COMPARE/PWM (CCP) MODULE(S)
CCP2 Module Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. Additional information on the CCP module is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes. The operation of CCP1 is identical to that of CCP2, with the exception of the special trigger. Therefore, operation of a CCP module in the following sections is described with respect to CCP1. Table 7-2 shows the interaction of the CCP modules. CCP1 Module Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable.
TABLE 7-1:
CCP MODE - TIMER RESOURCE
Timer Resource Timer1 Timer1 Timer2
CCP Mode Capture Compare PWM
TABLE 7-2:
INTERACTION OF TWO CCP MODULES
Interaction Same TMR1 time-base. The compare should be configured for the special event trigger, which clears TMR1. The compare(s) should be configured for the special event trigger, which clears TMR1. The PWMs will have the same frequency, and update rate (TMR2 interrupt). None None
CCPx Mode CCPy Mode Capture Capture Compare PWM PWM PWM Capture Compare Compare PWM Capture Compare
FIGURE 7-1:
U-0 -- bit7 U-0 --
CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
R/W-0 CCPxX R/W-0 R/W-0 CCPxY CCPxM3 R/W-0 CCPxM2 R/W-0 R/W-0 CCPxM1 CCPxM0 bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7-6: Unimplemented: Read as '0' bit 5-4: CCPxX:CCPxY: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode
(c) 1998 Microchip Technology Inc.
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7.1 Capture Mode
7.1.4 CCP PRESCALER In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. 7.1.1 CCP PIN CONFIGURATION
EXAMPLE 7-1:
CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition.
CCP1CON NEW_CAPT_PS
MOVWF
CCP1CON
FIGURE 7-2:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set flag bit CCP1IF (PIR1<2>)
Prescaler / 1, 4, 16 RC2/CCP1 Pin and edge detect
CCPR1H Capture Enable TMR1H CCP1CON<3:0> Q's
CCPR1L
TMR1L
7.1.2
TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. 7.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode.
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7.2 Compare Mode
7.2.1 CCP PIN CONFIGURATION In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: * driven High * driven Low * remains Unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch. TIMER1 MODE SELECTION
7.2.2
FIGURE 7-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 7.2.3 SOFTWARE INTERRUPT MODE
Special event trigger will reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion Special Event Trigger (CCP2 only) Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S Output Logic match RC2/CCP1 R Pin TRISC<2> Output Enable CCP1CON<3:0> Mode Select Comparator TMR1H TMR1L
When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). 7.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special trigger output of CCP2 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP2 module will not set interrupt flag bit TMR1IF (PIR1<0>).
TABLE 7-3:
Address
0Bh,8Bh 0Ch 8Ch 87h 0Eh 0Fh 10h 15h 16h 17h
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Bit 7
GIE
(1) (1)
Name
INTCON PIR1 PIE1 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON
Bit 6
PEIE ADIF ADIE
Bit 5
T0IE
(1) (1)
Bit 4
INTE
(1) (1)
Bit 3
RBIE SSPIF SSPIE
Bit 2
T0IF CCP1IF CCP1IE
Bit 1
INTF TMR2IF TMR2IE
Bit 0
RBIF
Value on POR, BOR
Value on all other resets
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
PORTC Data Direction Register Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- CCP1X CCP1Y
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: These bits/registers are reserved, maintain as '0'.
(c) 1998 Microchip Technology Inc.
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7.3 PWM Mode
7.3.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] 4 TOSC (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 6.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE
Figure 7-4 shows a simplified block diagram of the CCP module in PWM mode. For a step by step procedure on how to set up the CCP module for PWM operation, see Section 7.3.3.
FIGURE 7-4:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty cycle registers CCPR1L
7.3.2
CCPR1H (Slave)
Comparator
R
Q RC2/CCP1
TMR2
(Note 1) S TRISC<2> Clear Timer, CCP1 pin and latch D.C.
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM DUTY CYCLE = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 PRESCALE VALUE) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared.= Maximum PWM resolution (bits) for a given PWM frequency: FOSC log --------------- FPWM -bits = ---------------------------log ( 2 ) Note:
Comparator
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 7-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/ period).
FIGURE 7-5:
PWM OUTPUT
Period
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
For an example PWM period and duty cycle calculation, see the PICmicroTM Mid-Range Reference Manual (DS33023).
DS30605A-page 48
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7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
TABLE 7-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 0xFF 10 4 0xFF 10 1 0xFF 10 1 0x3F 8 1 0x1F 7 1 0x17 5.5
Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 7-5:
Address 0Bh,8Bh 0Ch 8Ch Name
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 GIE
(1) (1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE
(1) (1)
Bit 4 INTE
(1) (1)
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF CCP1IF CCP1IE
Bit 1 INTF TMR2IF TMR2IE
Bit 0 RBIF TMR1IF TMR1IE
Value on POR, BOR
Value on all other resets
INTCON PIR1 PIE1
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000
87h
11h 92h 12h 15h 16h 17h Legend: Note 1:
TRISC
TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON
PORTC Data Direction Register
Timer2 module's register Timer2 module's period register --
1111 1111 1111 1111
0000 0000 0000 0000 1111 1111 1111 1111
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- CCP1X CCP1Y
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. These bits/registers are reserved, maintain as '0'.
(c) 1998 Microchip Technology Inc.
DS30605A-page 49
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NOTES:
DS30605A-page 50
(c) 1998 Microchip Technology Inc.
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8.0
8.1
SYNCHRONOUS SERIAL PORT (SSP) MODULE
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) For more information on SSP operation (including an I2C Overview), refer to the PICmicroTM Mid-Range Reference Manual (DS33023). Also, refer to Application Note AN578, "Use of the SSP Module in the I 2C MultiMaster Environment."
(c) 1998 Microchip Technology Inc.
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FIGURE 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0 SMP bit7 CKE
R-0 D/A
R-0 P
R-0 S
R-0 R/W
R-0 UA
R-0 BF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
SMP: SPI data input sample phase SPI Master Operation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode CKE: SPI Clock Edge Select CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
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PIC16C63A/65B/73B/74B
FIGURE 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0 WCOL bit7
R/W-0 SSPOV
R/W-0 SSPEN
R/W-0 CKP
R/W-0 SSPM3
R/W-0 SSPM2
R/W-0 SSPM1
R/W-0 SSPM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow
bit 6:
bit 5:
SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master operation, clock = FOSC/4 0001 = SPI master operation, clock = FOSC/16 0010 = SPI master operation, clock = FOSC/64 0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master operation (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
(c) 1998 Microchip Technology Inc.
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8.2 SPI Mode
Note: When the SPI is in Slave Mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set to VDD. If the SPI is used in Slave Mode with CKE = '1', then the SS pin control must be enabled. This section contains register definitions and operational characteristics of the SPI module. Additional information on SPI operation may be found in the PICmicroTM Mid-Range Reference Manual (DS33023). 8.2.1 OPERATION OF SSP MODULE IN SPI MODE
Note:
FIGURE 8-3:
A block diagram of the SSP Module in SPI Mode is shown in Figure 8-3. The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) RC5/SDO RC4/SDI/SDA RC3/SCK/SCL
RC4/SDI/SDA RC5/SDO
SSP BLOCK DIAGRAM (SPI MODE)
Internal data bus Read SSPBUF reg Write
Additionally a fourth pin may be used when in a slave mode of operation: * Slave Select (SS) RA5/SS/AN4 When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: Master Operation (SCK is the clock output) Slave Mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock Edge (Output data on rising/falling edge of SCK) * Clock Rate (master operation only) * Slave Select Mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: * SDI must have TRISC<4> set * SDO must have TRISC<5> cleared * SCK (master operation) must have TRISC<3> cleared * SCK (Slave mode) must have TRISC<3> set * SS must have TRISA<5> set * * * *
SSPSR reg bit0 shift clock
SS Control Enable RA5/SS/AN4 Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TRISC<3>
TMR2 output 2 Prescaler TCY 4, 16, 64
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TABLE 8-1:
Address 0Bh,8Bh 0Ch 8Ch 87h 13h 14h 85h 94h Name INTCON PIR1 PIE1 TRISC SSPBUF
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7 GIE
(1) (1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE
(1) (1)
Bit 4 INTE
(1) (1)
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF
Bit 1 INTF
Bit 0 RBIF
Value on: POR, BOR
Value on all other resets
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM1 SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 UA BF 0000 0000 0000 0000
PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register SSPOV SSPEN -- CKE CKP SSPM3 SSPM2
SSPCON WCOL TRISA SSPSTAT -- SMP
PORTA Data Direction Register D/A P S R/W
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Always maintain these bits clear.
(c) 1998 Microchip Technology Inc.
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8.3 SSP I 2C Operation
The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>). The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address), with start and stop bit interrupts enabled * I 2C Slave mode (10-bit address), with start and stop bit interrupts enabled * I 2C Firmware controlled master operation, slave is idle Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. Additional information on SSP I2C operation may be found in the PICMicroTM Mid-Range Reference Manual (DS33023). 8.3.1 SLAVE MODE
FIGURE 8-4:
SSP BLOCK DIAGRAM (I2C MODE)
Internal data bus Read SSPBUF reg shift clock SSPSR reg Write
RC3/SCK/SCL
In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register.
Addr Match
RC4/ SDI/ SDA
MSb
LSb
Match detect
There are certain conditions that will cause the SSP module not to give this ACK pulse. These are if either (or both): a) The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received.
SSPADD reg Start and Stop bit detect Set, Reset S, P bits (SSPSTAT reg)
b)
The SSP module has five registers for I2C operation. These are the: SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible * SSP Address Register (SSPADD) * * * *
In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 8-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification as well as the requirement of the SSP module is shown in timing parameter #100 and parameter #101.
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(c) 1998 Microchip Technology Inc.
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8.3.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth SCL pulse. `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows with steps 7- 9 for slave-transmitter: 1. 2. Receive first (high) byte of Address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated START condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
3. 4. 5.
6. 7. 8. 9.
In 10-bit address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte would equal
TABLE 8-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes
Status Bits as Data Transfer is Received BF 0 1 1 0
Note:
SSPOV 0 0 1 1
SSPSR SSPBUF Yes No No Yes
Generate ACK Pulse Yes No No No
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
(c) 1998 Microchip Technology Inc.
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8.3.1.2 RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte.
FIGURE 8-5:
I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
Receiving Address Receiving Data R/W=0 Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL
SSPIF (PIR1<3>)
Cleared in software
Bus Master terminates transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
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8.3.1.3 TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 8-6). An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 8-6:
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK
SDA
A7
A6
A5
A4
A3
A2
SCL
S
1 2 Data in sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>) BF (SSPSTAT<0>)
cleared in software
SSPBUF is written in software CKP (SSPCON<4>)
From SSP interrupt service routine
Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set)
(c) 1998 Microchip Technology Inc.
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8.3.2 MASTER OPERATION 8.3.3 MULTI-MASTER OPERATION Master operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle and both the S and P bits are clear. In master operation, the SCL and SDA lines are manipulated in firmware by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit. The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): * START condition * STOP condition * Data transfer byte transmitted/received Master operation can be done with either the slave mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt. For more information on master operation, see AN554 - Software Implementation of I2C Bus Master. In multi-master operation, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are: * Address Transfer * Data Transfer When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. For more information on master operation, see AN578 - Use of the SSP Module in the of I2C Multi-Master Environment.
TABLE 8-3:
Address Name
REGISTERS ASSOCIATED WITH I2C OPERATION
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 000x 0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 1111 1111 Value on all other resets 0000 000u 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 1111 1111
0Bh, 8Bh 0Ch 8Ch 13h 93h 14h 94h 87h
INTCON PIR1 PIE1
GIE
(1) (1)
PEIE ADIF ADIE
T0IE
(1) (1)
INTE
(1) (1)
RBIE
T0IF
INTF
RBIF
SSPIF CCP1IF TMR2IF TMR1IF SSPIE CCP1IE TMR2IE TMR1IE
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register SSPADD Synchronous Serial Port (I2C mode) Address Register SSPCON SSPSTAT TRISC WCOL SMP SSPOV SSPEN CKE D/A CKP P SSPM3 SSPM2 SSPM1 SSPM0 S R/W UA BF
PORTC Data Direction register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: These bits are unimplemented, read as '0'.
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PIC16C63A/65B/73B/74B
9.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The USART can be configured in the following modes: * Asynchronous (full duplex) * Synchronous - Master (half duplex) * Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to be set in order to configure pins RC6/TX/CK and RC7/ RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc.
FIGURE 9-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 CSRC bit7
R/W-0 TX9
R/W-0 TXEN
R/W-0 SYNC
U-0 --
R/W-0 BRGH
R-1 TRMT
R/W-0 TX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
CSRC: Clock Source Select bit Asynchronous mode Don't care Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as '0' BRGH: High Baud Rate Select bit Asynchronous mode 1 = High speed 0 = Low speed Synchronous mode Unused in this mode
bit 5:
bit 4:
bit 3: bit 2:
bit 1:
TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of transmit data. Can be parity bit.
bit 0:
(c) 1998 Microchip Technology Inc.
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FIGURE 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 SPEN bit7
R/W-0 RX9
R/W-0 SREN
R/W-0 CREN
U-0 --
R-0 FERR
R-0 OERR
R-x RX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode Don't care Synchronous mode - master 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave Unused in this mode
bit 6:
bit 5:
bit 4:
CREN: Continuous Receive Enable bit Asynchronous mode 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive
bit 3: bit 2:
Unimplemented: Read as '0' FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of received data (Can be parity bit)
bit 1:
bit 0:
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(c) 1998 Microchip Technology Inc.
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9.1 USART Baud Rate Generator (BRG) EXAMPLE 9-1:
Desired Baud rate 9600 X = Error = = =
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In asynchronous mode bit BRGH (TXSTA<2>) also controls the baud rate. In synchronous mode bit BRGH is ignored. Table 9-1 shows the formula for computation of the baud rate for different USART modes which only apply in master mode (internal clock). Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be calculated using the formula in Table 9-1. From this, the error in baud rate can be determined. Example 9-1 shows the calculation of the baud rate error for the following conditions: FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0
CALCULATING BAUD RATE ERROR
=Fosc / (64 (X + 1)) =16000000 /(64 (X + 1)) =25.042 = 25 9615 (Calculated Baud Rate-Desired Baud Rate) Desired Baud Rate (9615 - 9600) / 9600 0.16%
Calculated Baud Rate =16000000 / (64 (25 + 1))
It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 9.1.1 SAMPLING
The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
TABLE 9-1:
SYNC
0 1
BAUD RATE FORMULA
BRGH = 0 (Low Speed) BRGH = 1 (High Speed) Baud Rate= FOSC/(16(X+1)) NA
(Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) X = value in SPBRG (0 to 255)
TABLE 9-2:
Address 98h 18h 99h
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7 CSRC SPEN Bit 6 TX9 RX9 Bit 5 TXEN Bit 4 SYNC Bit 3 -- Bit 2 BRGH FERR Bit 1 TRMT Bit 0 TX9D Value on POR, BOR
0000 -010
Name TXSTA RCSTA SPBRG
Value on all other resets
0000 -010 0000 -00x 0000 0000
SREN CREN --
OERR RX9D 0000 -00x
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
(c) 1998 Microchip Technology Inc.
DS30605A-page 63
PIC16C63A/65B/73B/74B
TABLE 9-3:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW KBAUD NA NA NA NA 19.53 76.92 96.15 294.1 500 5000 19.53
BAUD RATES FOR SYNCHRONOUS MODE
% +1.73 +0.16 +0.16 -1.96 0 16 MHz value % (decimal) KBAUD 255 64 51 16 9 0 255 NA NA NA NA 19.23 76.92 95.24 307.69 500 4000 15.625 4 MHz % +0.16 +0.16 +0.16 +4.17 +0.16 +0.16 -0.79 +2.56 0 SPBRG 10 MHz value % (decimal) KBAUD 207 51 41 12 7 0 255 NA NA NA 9.766 19.23 75.76 96.15 312.5 500 2500 9.766 +1.73 +0.16 -1.36 +0.16 +4.17 0 SPBRG 7.15909 MHz value % (decimal) KBAUD 255 129 32 25 7 4 0 255 NA NA NA 9.622 19.24 77.82 94.20 298.3 NA 1789.8 6.991 +0.23 +0.23 +1.32 -1.88 -0.57 SPBRG value (decimal) 185 92 22 18 5 0 255 SPBRG 32.768 kHz value % (decimal) KBAUD 207 103 25 12 2 0 255 0.303 1.170 NA NA NA NA NA NA NA 8.192 0.032 +1.14 -2.48 SPBRG value (decimal) 26 6 0 255
FOSC = 20 MHz SPBRG
FOSC = 5.0688 MHz
KBAUD NA NA NA 9.6 19.2 79.2 97.48 316.8 NA 1267 4.950 % 0 0 +3.13 +1.54 +5.60 131 65 15 12 3 0 255
SPBRG KBAUD NA NA NA 9.615 19.231 76.923 1000 NA NA 100 3.906
SPBRG 3.579545 MHz value % (decimal) KBAUD 103 51 12 9 0 255 NA NA NA 9.622 19.04 74.57 99.43 298.3 NA 894.9 3.496 +0.23 -0.83 -2.90 +3.57 -0.57 -
SPBRG 1 MHz value % (decimal) KBAUD 92 46 11 8 2 0 255 NA 1.202 2.404 9.615 19.24 83.34 NA NA NA 250 0.9766 +0.16 +0.16 +0.16 +0.16 +8.51 -
TABLE 9-4:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
16 MHz % NA 1.202 2.404 9.615 19.23 83.33 NA NA NA 250 0.977 4 MHz % 0.3005 1.202 2.404 NA NA NA NA NA NA 62.500 3.906 -0.17 +1.67 +1.67 +0.16 +0.16 +0.16 +0.16 +8.51 % value (decimal) 255 129 32 15 3 2 0 0 255 SPBRG value (decimal) 207 103 25 12 2 0 255 SPBRG value (decimal) 207 51 25 0 255 10 MHz % NA 1.202 2.404 9.766 19.53 78.13 NA NA NA 156.3 0.6104 +0.16 +0.16 +1.73 +1.73 +1.73 SPBRG value (decimal) 129 64 15 7 1 0 255 SPBRG value (decimal) 185 46 22 5 2 0 255 7.15909 MHz % NA 1.203 2.380 9.322 18.64 NA NA NA NA 111.9 0.437 1 MHz % 0.300 1.202 2.232 NA NA NA NA NA NA 15.63 0.0610 +0.16 +0.16 -6.99 +0.23 -0.83 -2.90 -2.90 SPBRG value (decimal) 92 46 11 5 0 255 SPBRG value (decimal) 51 12 6 0 255 32.768 kHz % 0.256 NA NA NA NA NA NA NA NA 0.512 0.0020 -14.67 SPBRG value (decimal) 1 0 255
FOSC = 20 MHz SPBRG
NA 1.221 2.404 9.469 19.53 78.13 104.2 312.5 NA 312.5 1.221 +1.73 +0.16 -1.36 +1.73 +1.73 +8.51 +4.17 -
FOSC = 5.0688 MHz % 0.31 1.2 2.4 9.9 19.8 79.2 NA NA NA 79.2 0.3094 +3.13 0 0 +3.13 +3.13 +3.13 SPBRG 255 65 32 7 3 0 0 255
3.579545 MHz % 0.301 1.190 2.432 9.322 18.64 NA NA NA NA 55.93 0.2185 +0.23 -0.83 +1.32 -2.90 -2.90 -
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PIC16C63A/65B/73B/74B
TABLE 9-5:
BAUD RATE (K) 9.6 19.2 38.4 57.6 115.2 250 625 1250 BAUD RATE (K) 9.6 19.2 38.4 57.6 115.2 250 625 1250
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
% SPBRG value (decimal) 129 64 32 21 10 4 1 0 SPBRG value (decimal) 32 16 7 5 2 16 MHz % 9.615 19.230 38.461 58.823 111.111 250 NA NA 4 MHz % NA 1.202 2.403 9.615 19.231 NA NA NA +0.17 +0.13 +0.16 +0.16 +0.16 +0.16 +0.16 +2.12 -3.55 0 SPBRG value (deci103 51 25 16 8 3 SPBRG value (decimal) 207 103 25 12 10 MHz % 9.615 18.939 39.062 56.818 125 NA 625 NA +0.16 -1.36 +1.7 -1.36 +8.51 0 SPBRG value (decimal) 64 32 15 10 4 0 SPBRG value (decimal) 22 11 5 3 1 0 7.16 MHz % 9.520 19.454 37.286 55.930 111.860 NA NA NA 1 MHz % 8.928 20.833 31.25 62.5 NA NA NA NA -6.99 +8.51 -18.61 +8.51 -0.83 +1.32 -2.90 -2.90 -2.90 SPBRG value (deci46 22 11 7 3 SPBRG value (decimal) 6 2 1 0 32.768 kHz % NA NA NA NA NA NA NA NA SPBRG value (decimal) -
FOSC = 20 MHz
9.615 19.230 37.878 56.818 113.636 250 625 1250 +0.16 +0.16 -1.36 -1.36 -1.36 0 0 0
FOSC = 5.068
% 9.6 18.645 39.6 52.8 105.6 NA NA NA 0 -2.94 +3.12 -8.33 -8.33 -
3.579 MHz % 9.727 18.643 37.286 55.930 111.860 +1.32 -2.90 -2.90 -2.90 -2.90
223.721 -10.51 NA NA -
(c) 1998 Microchip Technology Inc.
DS30605A-page 65
PIC16C63A/65B/73B/74B
9.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-tozero (NRZ) format (one start bit, eight or nine data bits and one stop bit). The most common data format is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver USART ASYNCHRONOUS TRANSMITTER (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory so it is not available to the user. Note 2: Flag bit TXIF is set when enable bit TXEN is set. Steps to follow when setting up an asynchronous transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 9.1) Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission).
2. 3. 4. 5. 6. 7.
9.2.1
The USART transmitter block diagram is shown in Figure 9-3. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register
FIGURE 9-3:
USART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN *** TSR register TXREG register 8 LSb 0 Pin Buffer and Control RC6/TX/CK pin
DS30605A-page 66
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 9-4:
Write to TXREG BRG output (shift clock) RC6/TX/CK (pin) TXIF bit (Transmit buffer reg. empty flag) Word 1
ASYNCHRONOUS TRANSMISSION
Start Bit
Bit 0
Bit 1 WORD 1
Bit 7/8
Stop Bit
TRMT bit (Transmit shift reg. empty flag)
WORD 1 Transmit Shift Reg
FIGURE 9-5:
Write to TXREG BRG output (shift clock)
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Word 1 Word 2
RC6/TX/CK (pin) TXIF bit (interrupt reg. flag)
Start Bit
Bit 0
Bit 1 WORD 1
Bit 7/8
Stop Bit
Start Bit WORD 2
Bit 0
TRMT bit (Transmit shift reg. empty flag)
WORD 1 Transmit Shift Reg.
WORD 2 Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 9-6:
Address Name 0Ch 18h 19h 8Ch 98h PIR1 RCSTA
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 PSPIF(1) SPEN Bit 6 Bit 5 Bit 4 TXIF Bit 3 Bit 2 Bit 1 TMR2IF OERR Bit 0 TMR1IF RX9D Value on POR, BOR 0000 0000 0000 -00x 0000 0000 TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 Value on all other Resets 0000 0000 0000 -00x 0000 0000 0000 0000
ADIF(2) RCIF RX9 SREN
SSPIF CCP1IF FERR
CREN --
TXREG USART Transmit Register PIE1 PSPIE(1) ADIE(2) RCIE
0000 -010 0000 -010 TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 0000 0000 0000 0000 99h SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: PORTD and PORTE not implemented on the PIC16C63A/73B, maintain as '0'. 2: A/D not implemented on the PIC16C63A/65B, maintain as '0'.
(c) 1998 Microchip Technology Inc.
DS30605A-page 67
PIC16C63A/65B/73B/74B
9.2.2 USART ASYNCHRONOUS RECEIVER 3. 4. 5. 6. The receiver block diagram is shown in Figure 9-6. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. Steps to follow when setting up an Asynchronous Reception: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 9.1). Enable the asynchronous serial port by clearing bit SYNC, and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing enable bit CREN.
7.
8. 9.
2.
FIGURE 9-6:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN SPBRG / 64 or / 16 OERR FERR
MSb Stop (8) 7
RSR register *** 1
LSb 0 Start
Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery
RX9
SPEN
RX9D
RCREG register FIFO
8 Interrupt RCIF RCIE Data Bus
FIGURE 9-7:
RX (pin) Rcv shift reg Rcv buffer reg Read Rcv buffer reg RCREG RCIF (interrupt flag) OERR bit CREN
ASYNCHRONOUS RECEPTION
Start bit bit0 bit1 bit7/8 Stop bit Start bit bit0 bit7/8 Stop bit Start bit bit7/8 Stop bit
WORD 1 RCREG
WORD 2 RCREG
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
DS30605A-page 68
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 9-7:
Address Name 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 PSPIF(1) SPEN Bit 6 ADIF(2) RX9 Bit 5 RCIF SREN Bit 4 TXIF CREN Bit 3 Bit 2 Bit 1 TMR2IF OERR Bit 0 TMR1IF RX9D Value on POR, BOR 0000 0000 0000 -00x 0000 0000 TXIE SYNC SSPIE CCP1IE TMR2IE -- BRGH TRMT TMR1IE TX9D 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
SSPIF CCP1IF -- FERR
RCREG USART Receive Register PIE1 TXSTA SPBRG PSPIE(1) CSRC ADIE(2) RCIE TX9 TXEN
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B, always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B, always maintain these bits clear.
(c) 1998 Microchip Technology Inc.
DS30605A-page 69
PIC16C63A/65B/73B/74B
9.3 USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in a half-duplex manner, i.e. transmission and reception do not occur at the same time. When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>). 9.3.1 USART SYNCHRONOUS MASTER TRANSMISSION enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. TRMT is a read only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. Steps to follow when setting up a Synchronous Master Transmission: 1. 2. 3. 4. 5. 6. 7. Initialize the SPBRG register for the appropriate baud rate (Section 9.1). Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register.
The USART transmitter block diagram is shown in Figure 9-3. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one Tcycle), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be
TABLE 9-8:
Address 0Ch 18h 19h 8Ch 98h Name PIR1 RCSTA TXREG PIE1 TXSTA
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 PSPIF(1) SPEN Bit 6 ADIF(2) RX9 Bit 5 RCIF SREN Bit 4 TXIF CREN Bit 3 SSPIF -- Bit 2 CCP1IF FERR Bit 1 TMR2IF OERR Bit 0 TMR1IF RX9D Value on POR, BOR 0000 0000 0000 -00x 0000 0000 TXIE SYNC SSPIE -- CCP1IE BRGH TMR2IE TRMT TMR1IE TX9D 0000 0000 0000 -010 Value on all other Resets 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010
USART Transmit Register PSPIE(1) CSRC ADIE(2) TX9 RCIE TXEN
0000 0000 0000 0000 99h SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B, always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B, always maintain these bits clear.
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(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 9-8: SYNCHRONOUS TRANSMISSION
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg
Write word1
Bit 0
Bit 1 WORD 1
Bit 2
Bit 7
Bit 0
Bit 1 WORD 2
Bit 7
Write word2
TXIF bit
(Interrupt flag) TRMT TRMT bit
TXEN bit
'1'
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
'1'
FIGURE 9-9:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit0 bit1 bit2 bit6 bit7
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
(c) 1998 Microchip Technology Inc.
DS30605A-page 71
PIC16C63A/65B/73B/74B
9.3.2 USART SYNCHRONOUS MASTER RECEPTION Ensure bits CREN and SREN are clear. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 3. 4.
Once synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. Steps to follow when setting up a Synchronous Master Reception: 1. 2. Initialize the SPBRG register for the appropriate baud rate. (Section 9.1) Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC.
TABLE 9-9:
Address 0Ch 18h 1Ah 8Ch 98h Name PIR1 RCSTA
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 PSPIF(1) SPEN Bit 6 ADIF(2) RX9 Bit 5 RCIF SREN Bit 4 TXIF CREN Bit 3 SSPIF -- Bit 2 CCP1IF FERR Bit 1 TMR2IF OERR Bit 0 TMR1IF RX9D Value on: POR, BOR 0000 0000 0000 -00x 0000 0000 TXIE SYNC SSPIE -- CCP1IE BRGH TMR2IE TRMT TMR1IE TX9D 0000 0000 0000 -010 Value on all other Resets 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010
RCREG PIE1 TXSTA
USART Receive Register PSPIE(1) CSRC ADIE(2) TX9 RCIE TXEN
0000 0000 0000 0000 99h SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Allways maintain these bits clear.
FIGURE 9-10: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' RCIF bit (interrupt) Read RXREG
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
'0'
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'.
DS30605A-page 72
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.4 USART Synchronous Slave Mode
9.4.2 USART SYNCHRONOUS SLAVE RECEPTION Synchronous slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 9.4.1 USART SYNCHRONOUS SLAVE TRANSMIT
The operation of the synchronous master and slave modes is identical except in the case of the SLEEP mode and bit SREN, which is a "don't care" in slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h). Steps to follow when setting up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN.
The operation of the synchronous master and slave modes are identical, except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
2. 3. 4. 5.
e)
6.
Steps to follow when setting up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. 7. 8.
2. 3. 4. 5. 6. 7.
(c) 1998 Microchip Technology Inc.
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TABLE 9-10:
Address 0Ch 18h 19h 8Ch 98h 99h Name PIR1 RCSTA TXREG PIE1 TXSTA SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7 PSPIF(1) SPEN Bit 6 ADIF(2) RX9 Bit 5 RCIF SREN Bit 4 TXIF CREN Bit 3 SSPIF -- Bit 2 CCP1IF FERR Bit 1 TMR2IF OERR Bit 0 TMR1IF RX9D Value on POR, BOR 0000 0000 0000 -00x 0000 0000 TXIE SYNC SSPIE -- CCP1IE BRGH TMR2IE TRMT TMR1IE TX9D 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
USART Transmit Register PSPIE(1) CSRC ADIE(2) TX9 RCIE TXEN
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Always maintain these bits clear.
TABLE 9-11:
Address 0Ch 18h 1Ah 8Ch 98h Name PIR1 RCSTA
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Bit 7 PSPIF(1) SPEN Bit 6 ADIF(2) RX9 Bit 5 RCIF SREN Bit 4 TXIF CREN Bit 3 SSPIF -- Bit 2 CCP1IF FERR Bit 1 TMR2IF OERR Bit 0 TMR1IF RX9D Value on POR, BOR 0000 0000 0000 -00x 0000 0000 TXIE SYNC SSPIE -- CCP1IE BRGH TMR2IE TRMT TMR1IE TX9D 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010
RCREG PIE1 TXSTA
USART Receive Register PSPIE(1) CSRC ADIE(2) TX9 RCIE TXEN
0000 0000 99h SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Always maintain these bits clear.
DS30605A-page 74
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
10.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
Additional information on the A/D module is available in the PICmicroTM Mid-Range Reference Manual, (DS33023). The A/D module has three registers. These registers are: * A/D Result Register (ADRES) * A/D Control Register 0 (ADCON0) * A/D Control Register 1 (ADCON1) A device reset forces all registers to their reset state. This forces the A/D module to be turned off and any conversion is aborted. The ADCON0 register, shown in Figure 10-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 10-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as digital I/O.
This section applies to the PIC16C73B and PIC16C74B only. The analog-to-digital (A/D) converter module has five inputs for the PIC16C73B, and eight for the PIC16C74B. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD) or the voltage level on the RA3/AN3/VREF pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator.
FIGURE 10-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0 ADCS1 ADCS0 bit7 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an internal RC oscillator) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: bit 0: Unimplemented: Read as '0' ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current
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FIGURE 10-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x A = Analog input D = Digital I/O RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D VREF VDD RA3 VDD RA3 VDD RA3 VDD
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The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 10-3. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 10.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins / voltage reference / and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts.
3. 4. 5.
FIGURE 10-3: A/D BLOCK DIAGRAM
CHS2:CHS0
111 110 101 100 VIN (Input voltage) 011 010 A/D Converter 001
RE2/AN7(1) RE1/AN6(1) RE0/AN5(1) RA5/AN4 RA3/AN3/VREF RA2/AN2 RA1/AN1
VDD VREF (Reference voltage) PCFG2:PCFG0 Note 1: Available on the PIC16C74B only. 000 or 010 or 100 001 or 011 or 101
000 RA0/AN0
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10.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 10-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, TACQ, see the PICmicroTM Mid-Range Reference Manual, (DS33023). This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy. Note: When the conversion is started, the holding capacitor is disconnected from the input pin.
FIGURE 10-4: ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS CHOLD = DAC capacitance = 51.2 pF VSS Legend CPIN = input capacitance = threshold voltage VT I leakage = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
Rs
ANx
VA
CPIN 5 pF
VT = 0.6V
I leakage 500 nA
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch ( k )
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10.2 Selecting the A/D Conversion Clock 10.3 Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: * * * * 2TOSC 8TOSC 32TOSC Internal RC oscillator The ADCON1, TRISA, and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins) may cause the input buffer to consume current that is out of the devices specification.
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 10-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 10-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency 20 MHz 100 ns(2) ns(2) 400 1.6 s 5 MHz 400 1.6 s ns(2) 1.25 MHz 1.6 s 6.4 s 25.6 s(3) s(1,4) 333.33 kHz 6 s 24 s(3) 96 s(3)
AD Clock Source (TAD) Operation 2TOSC 8TOSC 32TOSC RC(5) Legend: Note 1: 2: 3: 4: ADCS1:ADCS0 00 01 10 11
6.4 s s(1,4)
2-6 2-6 2 - 6 s(1) 2-6 Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. s(1,4)
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10.4
Note:
A/D Conversions
The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
10.5
Use of the CCP Trigger
An A/D conversion can be started by the "special event trigger" of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter.
TABLE 10-2:
Address Name
SUMMARY OF A/D REGISTERS
Bit 7 GIE PSPIF(1) PSPIE(1) -- -- Bit 6 PEIE ADIF ADIE -- -- Bit 5 T0IE RCIF RCIE -- -- Bit 4 INTE TXIF TXIE -- -- Bit 3 RBIE SSPIF SSPIE -- -- Bit 2 T0IF CCP1IF CCP1IE -- -- Bit 1 INTF Bit 0 RBIF Value on POR, BOR 0000 000x Value on all other Resets 0000 000u 0000 0000 0000 0000 ---- ---0 ---- ---0 uuuu uuuu 0000 00-0 ---- -000 --0u 0000 --11 1111 ---- -uuu 0000 -111
0Bh,8Bh INTCON 0Ch 8Ch 0Dh 8Dh 1Eh 1Fh 9Fh 05h 85h 09h 89h PIR1 PIE1 PIR2 PIE2 ADRES ADCON0 ADCON1 PORTA TRISA PORTE TRISE
TMR2IF TMR1IF 0000 0000 TMR2IE TMR1IE 0000 0000 -- -- CCP2IF ---- ---0 CCP2IE ---- ---0 xxxx xxxx
A/D Result Register ADCS1 -- -- -- -- IBF ADCS0 -- -- -- -- OBF CHS2 -- RA5 -- IBOV CHS1 -- RA4 -- PSPMODE CHS0 -- RA3 -- -- GO/DON E PCFG2 RA2 -- PCFG1 RA1 ADON
0000 00-0
PCFG0 ---- -000 RA0 --0x 0000 --11 1111
PORTA Data Direction Register RE2 RE1 RE0
---- -xxx 0000 -111
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C73B. Always maintain these bits clear.
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11.0 SPECIAL FEATURES OF THE CPU
other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options. Additional information on special features is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
The PIC16C63A/65B/73B/74B devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * OSC Selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-circuit serial programming These devices have a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The
11.1
Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming.
FIGURE 11-1: CONFIGURATION WORD
CP1 bit13 CP0 CP1 CP0 CP1 CP0 -- BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 bit0
Register:CONFIG Address2007h
bit 13-8 5-4:
CP1:CP0: Code Protection bits (2) 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected Unimplemented: Read as '1' BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
bit 7: bit 6:
bit 3:
bit 2:
bit 1-0:
Note 1: 2:
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11.2
11.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 11-1:
Ranges Tested: Mode XT
CERAMIC RESONATORS
The PIC16CXXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR/CERAMIC RESONATORS
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz
OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
HS
These values are for design guidance only. See notes at bottom of page.
11.2.2
Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5%
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 11-2). The PIC16CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure 11-3).
All resonators used did not have built-in capacitors.
TABLE 11-2:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
Osc Type LP XT
FIGURE 11-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
C1(1) OSC1 To internal logic SLEEP PIC16CXXX
HS
4 MHz 8 MHz 20 MHz
XTAL OSC2 C2(1) Note1: 2: 3: RS(2)
RF(3)
These values are for design guidance only. See notes at bottom of page. Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM
See Table 11-1 and Table 11-2 for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the crystal chosen.
FIGURE 11-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
Clock from ext. system Open OSC1 PIC16CXXX OSC2
Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 11-1). 2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification.
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11.2.3 RC OSCILLATOR
11.3
Reset
For timing insensitive applications, the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 11-4 shows how the R/C combination is connected to the PIC16CXXX.
The PIC16CXXX differentiates between various kinds of reset: * * * * * * Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR)
FIGURE 11-4: RC OSCILLATOR MODE
VDD Rext OSC1 Cext VSS Fosc/4 Recommended values: OSC2/CLKOUT 3 k Rext 100 k Cext > 20pF Internal clock PIC16CXXX
Some registers are not affected in any reset condition. Their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR reset during SLEEP and Brownout Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 11-4. These bits are used in software to determine the nature of the reset. See Table 11-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 11-5. The PICmicros have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low.
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FIGURE 11-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset MCLR WDT Module VDD rise detect VDD Brown-out Reset OST/PWRT OST 10-bit Ripple counter OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter R Q Chip_Reset Power-on Reset S SLEEP WDT Time-out Reset
BODEN
Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
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11.4 Power-On Reset (POR) 11.5 Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified (parameter D004). For a slow rise time, see Figure 11-6. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions. The Power-up Timer provides a fixed nominal time-out (parameter #33) on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation. See DC parameters for details.
11.6
Oscillator Start-up Timer (OST)
FIGURE 11-6: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD D R R1 MCLR C PIC16CXXX
The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter #32). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
11.7
Brown-Out Reset (BOR)
Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below parameter D005 for greater than parameter #35, the brown-out situation will reset the chip. A reset may not occur if VDD falls below parameter D005 for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will then be invoked and will keep the chip in RESET an additional time delay (parameter #33). If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute the additional time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled.
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11.8 Time-out Sequence 11.9
On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 11-7, Figure 11-8, Figure 11-9 and Figure 11-10 depict timeout sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 11-9). This is useful for testing purposes or to synchronize more than one PIC16CXXX device operating in parallel. Table 11-5 shows the reset conditions for some special function registers, while Table 11-6 shows the reset conditions for all the registers.
Power Control/Status Register (PCON)
The Power Control/Status Register, PCON, has up to two bits, depending upon the device. Bit0 is Brown-out Reset Status bit, BOR. If the BODEN configuration bit is set, BOR is '1' on Power-on Reset. If the BODEN configuration bit is clear, BOR is unknown on Power-on Reset. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the BODEN configuration bit is clear). BOR must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.
TABLE 11-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 72 ms + 1024TOSC 72 ms PWRTE = 1 1024TOSC -- Brown-out 72 ms + 1024TOSC 72 ms Wake-up from SLEEP 1024TOSC --
Oscillator Configuration XT, HS, LP RC
TABLE 11-4:
POR 0 0 0 1 1 1 1 1 BOR x x x 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
TO 1 0 x 1 0 0 u 1 PD 1 x 0 1 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 11-5:
RESET CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1(1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP
Note 1:
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
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TABLE 11-6:
Register W INDF TMR0 PCL STATUS FSR PORTA(4) PORTB(5) PORTC(5) PORTD(5) PORTE(5) PCLATH INTCON
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B Power-on Reset, Brown-out Reset xxxx xxxx N/A xxxx xxxx 0000h 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx xxxx xxxx xxxx xxxx ---- -xxx ---0 0000 0000 000x --00 0000 -000 0000 0-00 0000 0000 0000 ---- ---0 xxxx xxxx xxxx xxxx --00 0000 0000 0000 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 -00x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 MCLR Resets WDT Reset uuuu uuuu N/A uuuu uuuu 0000h 000q quuu(3) uuuu uuuu --0u 0000 uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu ---0 0000 0000 000u --00 0000 -000 0000 0-00 0000 0000 0000 ---- ---0 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 -000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 0000 -00x 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu ---u uuuu uuuu uuuu(1) --uu uuuu(1) -uuu uuuu(1) u-uu uuuu(1) uuuu uuuu(1) ---- ---u(1) uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
PIR1
63A 63A
PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON
63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 11-5 for reset value for specific condition. 4: On any device reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch.
(c) 1998 Microchip Technology Inc.
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TABLE 11-6:
Register ADRES ADCON0 OPTION_REG TRISA TRISB TRISC TRISD TRISE
INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.'d)
Applicable Devices 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 63A 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 65B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 73B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B 74B Power-on Reset, Brown-out Reset xxxx xxxx 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 0000 -000 --00 0000 0-00 0000 -000 0000 0000 0000 ---- ---0 ---- --0q 1111 1111 0000 0000 0000 0000 0000 -010 0000 0000 ---- -000 MCLR Resets WDT Reset uuuu uuuu 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 0000 -000 --00 0000 0-00 0000 -000 0000 0000 0000 ---- ---0 ---- --uq 1111 1111 0000 0000 0000 0000 0000 -010 0000 0000 ---- -000 Wake-up via WDT or Interrupt uuuu uuuu uuuu uu-u uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu -uuu --uu uuuu u-uu uuuu -uuu uuuu uuuu uuuu ---- ---u ---- --uq 1111 1111 uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu ---- -uuu
PIE1
PIE2 PCON PR2 SSPADD SSPSTAT TXSTA SPBRG ADCON1
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 11-5 for reset value for specific condition. 4: On any device reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch.
FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
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FIGURE 11-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-10: SLOW RISE TIME (MCLR TIED TO VDD)
5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 0V 1V
(c) 1998 Microchip Technology Inc.
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11.10 Interrupts
The PIC16CXX family has up to 12 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset. The "return from interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts.
FIGURE 11-11: INTERRUPT LOGIC
PSPIF PSPIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE T0IF T0IE INTF INTE RBIF RBIE PEIE GIE Wake-up (If in SLEEP mode)
Interrupt to CPU
The following table shows which devices have which interrupts.
Device PIC16C63A PIC16C65B PIC16C73B PIC16C74B T0IF Yes Yes Yes Yes INTF Yes Yes Yes Yes RBIF Yes Yes Yes Yes PSPIF Yes Yes ADIF Yes Yes RCIF Yes Yes Yes Yes TXIF Yes Yes Yes Yes SSPIF Yes Yes Yes Yes CCP1IF Yes Yes Yes Yes TMR2IF Yes Yes Yes Yes TMR1IF Yes Yes Yes Yes CCP2IF Yes Yes Yes Yes
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11.10.1 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered; either rising if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 11.13 for details on SLEEP mode. 11.10.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 4.0) 11.10.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 3.2)
11.11
Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, i.e., W register and STATUS register. This will have to be implemented in software. Example 11-1 stores and restores the W and STATUS registers. The register, W_TEMP, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0. It must also be defined at 0xA0 in bank 1). The example: a) b) c) d) e) f) Stores the W register. Stores the STATUS register in bank 0. Stores the PCLATH register. Executes the interrupt service routine code (User-generated). Restores the STATUS register (and bank select bit). Restores the W and PCLATH registers.
EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF BCF MOVF MOVWF : :(ISR) : MOVF MOVWF SWAPF MOVWF SWAPF SWAPF W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH STATUS, IRP FSR, W FSR_TEMP ;Copy W to TEMP register, could be bank one or zero ;Swap status to be saved into W ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 ;Save status to bank zero STATUS_TEMP register ;Only required if using pages 1, 2 and/or 3 ;Save PCLATH into W ;Page zero, regardless of current page ;Return to Bank 0 ;Copy FSR to W ;Copy FSR from W to FSR_TEMP
PCLATH_TEMP, W PCLATH STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W
;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
(c) 1998 Microchip Technology Inc.
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11.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/ CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing configuration bit WDTE (Section 11.1). WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler if assigned to the WDT, and prevent it from timing out and generating a device RESET condition.
. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
FIGURE 11-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 4-2) 0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX WDT Enable Bit PSA To TMR0 (Figure 4-2) 0 MUX 1 PSA PS2:PS0
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
WDT Time-out
FIGURE 11-13: SUMMARY OF WATCHDOG TIMER REGISTERS
Address 2007h 81h Name Config. bits
OPTION_REG
Bit 7 (1) RBPU
Bit 6 BODEN(1) INTEDG
Bit 5 CP1 T0CS
Bit 4 CP0 T0SE
Bit 3 PWRTE(1) PSA
Bit 2 WDTE PS2
Bit 1 FOSC1 PS1
Bit 0 FOSC0 PS0
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 11-1 for operation of these bits.
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11.13 Power-down Mode (SLEEP)
Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 11.13.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 11.13.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change, or some Peripheral Interrupts.
External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. 7. 8. PSP read or write. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP capture mode interrupt. Special event trigger (Timer1 in asynchronous mode using an external clock). SSP (Start/Stop) bit detect interrupt. SSP transmit or receive in slave mode (SPI/I2C). USART RX or TX (synchronous slave mode). A/D conversion (when A/D clock source is RC).
(c) 1998 Microchip Technology Inc.
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FIGURE 11-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
11.14
Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip Technology does not recommend code protecting windowed devices.
11.15
ID Locations
Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used. For ROM devices, these values are submitted along with the ROM code.
11.16
In-Circuit Serial Programming
PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSPTM) Guide, (DS30277B).
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12.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 12-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 12-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. Table 12-2 lists the instructions recognized by the MPASM assembler. Figure 12-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16CXXX products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
FIGURE 12-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0 8 7 k (literal) 0 0
TABLE 12-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
0
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip Technology software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Program Counter Time-out bit Power-down bit
d
PC TO PD
k = 11-bit immediate value
The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s.
A description of each instruction is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
(c) 1998 Microchip Technology Inc.
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TABLE 12-2:
Mnemonic, Operands
PIC16CXXX INSTRUCTION SET
Description Cycles MSb 14-Bit Opcode LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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13.0
13.1
DEVELOPMENT SUPPORT
Development Tools
13.3
ICEPIC: Low-Cost PICmicroTM In-Circuit Emulator
The PICmicrTM microcontrollers are supported with a full range of hardware and software development tools: * PICMASTER(R)/PICMASTER CE Real-Time In-Circuit Emulator * ICEPICTM Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLABTM SIM Software Simulator * MPLAB-C17 (C Compiler) * Fuzzy Logic Development System (fuzzyTECH(R)-MP)
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT(R) through PentiumTM based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.
13.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode.
13.2
PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC14C000, PIC12CXXX, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLABTM Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows(R) 3.x environment were chosen to best make these features available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries.
13.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, low-cost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.
(c) 1998 Microchip Technology Inc.
DS30605A-page 97
PIC16C62X(A)
13.6 PICDEM-1 Low-Cost PICmicro Demonstration Board
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
13.9
MPLABTM Integrated Development Environment Software
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file * Transfer data dynamically via DDE (soon to be replaced by OLE) * Run up to four emulators on the same PC The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
13.7
PICDEM-2 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
13.8
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include
13.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PC-hosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from PICMASTER, Microchip's Universal Emulator System.
DS30605A-page 98
(c) 1998 Microchip Technology Inc.
PIC16C62X(A)
MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.
13.14
MP-DriveWayTM - Application Code Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually configure all the peripherals in a PICmicro device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip's MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.
13.15
SEEVAL(R) Evaluation and Programming System
13.11
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials. The Total EnduranceTM Disk is included to aid in trade-off analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
13.16
KEELOQ(R) Evaluation and Programming Tools
13.12
C Compiler (MPLAB-C17)
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
The MPLAB-C Code Development System is a complete `C' compiler and integrated development environment for Microchip's PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.
13.13
Fuzzy Logic Development System (fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
(c) 1998 Microchip Technology Inc.
DS30605A-page 99
PIC12C5XX
PIC14000
PIC16C5X
PIC16CXXX
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
PIC17C7XX
24CXX 25CXX 93CXX HCSXXX
TABLE 13-1
EMULATOR PRODUCTS
(PIC17C75X only)
DS30605A-page 100
PICMASTER(R)/ PICMASTER-CE In-Circuit Emulator
u u u u u u u
u
u
u
u
u
u
u
u
MPLABTM-ICE
u u
ICEPICTM Low-Cost In-Circuit Emulator
u
PIC16C62X(A)
SOFTWARE PRODUCTS
MPLABTM Integrated Development Environment
u u u u u u u u u u u u u u u u u
u
u
u
u
u
u
u
u
u u
MPLABTM C17 Compiler
fuzzyTECH(R)-MP Explorer/Edition Fuzzy Logic Dev. Tool
u
DEVELOPMENT TOOLS FROM MICROCHIP
MP-DriveWayTM Applications Code Generator
Total EnduranceTM Software Model
u
PROGRAMMERS
PICSTART(R)Plus Low-Cost Universal Dev. Kit
u u u u u u
u
u
u
u
u
u u
u u
u u
u u u u u u
PRO MATE(R) II Universal Programmer
u
KEELOQ(R) Programmer
DEMO BOARDS
SEEVAL(R) Designers Kit
PICDEM-1
u
u u u
u u
u
PICDEM-2
(c) 1998 Microchip Technology Inc.
PICDEM-3
PIC16C63A/65B/73B/74B
14.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings () Ambient temperature under bias............................................................................................................ .-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ..............................................................................................................20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ..............................................200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined) ..................................................................200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined) .............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE not available on the PIC16C63A/73B. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 14-1:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR MODES AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C63A-04 PIC16C65B-04 PIC16C73B-04 PIC16C74B-04 PIC16C63A-20 PIC16C65B-20 PIC16C73B-20 PIC16C74B-20 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. PIC16LC63A-04 PIC16LC65B-04 PIC16LC73B-04 PIC16LC74B-04 VDD: 2.5V to 5.5V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 2.5V to 5.5V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max.
OSC
Windowed (JW) Devices
RC
VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max.
VDD: 2.5V to 5.5V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 2.5V to 5.5V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.5V to 5.5V
XT
HS
Not recommended for use in IDD: 20 mA max. at 5.5V HS mode IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max.
VDD: 4.0V to 5.5V VDD: 2.5V to 5.5V VDD: 2.5V to 5.5V IDD: 52.5 A typ. Not recommended for use in IDD: 48 A max. at 32 kHz, IDD: 48 A max. at 32 kHz, at 32 kHz, 4.0V 3.0V 3.0V LP mode IPD: 0.9 A typ. at 4.0V IPD: 5 A max. at 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
LP
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 101
PIC16C63A/65B/73B/74B
14.1 DC Characteristics: PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended) PIC16C6A/65B/73B/74B-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Min 4.0 4.5 VBOR* Typ 1.5 VSS Max Units 5.5 5.5 5.5 V V V V V See section on Power-on Reset for details Conditions XT, RC and LP osc mode HS osc mode BOR enabled (Note 7)
DC CHARACTERISTICS
Param No. D001 D001A D002* D003
Sym VDD
Characteristic Supply Voltage
VDR VPOR
RAM Data Retention Voltage (Note 1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset voltage trip point Supply Current (Note 2, 5)
D004* SVDD D004A* D005 D010 VBOR IDD
0.05 TBD 3.65 -
2.7
4.35 5
V/ms PWRT enabled (PWRTE bit clear) PWRT disabled (PWRTE bit set) See section on Power-on Reset for details V mA BODEN bit set XT, RC osc modes FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc mode FOSC = 20 MHz, VDD = 5.5V VDD = 4.0V, WDT enabled,-40C to +85C VDD = 4.0V, WDT disabled, 0C to +70C VDD = 4.0V, WDT disabled,-40C to +85C VDD = 4.0V, WDT disabled,-40C to +125C
D013 D020 D021 D021B Module Differential Current (Note 6) D022* IWDT Watchdog Timer D022A* IBOR Brown-out Reset * Note1: 2: IPD Power-down Current (Note 3, 5)
-
10 10.5 1.5 1.5 2.5
20 42 16 19 19
mA A A A A
-
6.0 350
20 425
A A
WDTE bit set, VDD = 4.0V BODEN bit set, VDD = 5.0V
3: 4: 5: 6: 7:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30605A-page 102
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.2 DC Characteristics: PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial -40C TA +85C for industrial Min Typ Max Units Conditions 2.5 VBOR* 1.5 VSS 5.5 5.5 V V V V LP, XT, RC osc modes (DC - 4 MHz) BOR enabled (Note 7)
DC CHARACTERISTICS Param No. D001 D002* D003 Sym VDD VDR VPOR Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset voltage trip point Supply Current (Note 2, 5)
See section on Power-on Reset for details
D004* SVDD D004A* D005 D010 VBOR IDD
0.05 TBD 3.65 -
2.0
4.35 3.8
V/ms PWRT enabled (PWRTE bit clear) PWRT disabled (PWRTE bit set) See section on Power-on Reset for details V BODEN bit set mA A A A A XT, RC osc modes FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc mode FOSC = 32 kHz, VDD = 3.0V, WDT disabled VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C
D010A D020 D021 D021A IPD Power-down Current (Note 3, 5)
-
22.5 7.5 0.9 0.9
48 30 5 5
Module Differential Current (Note 6) 6.0 20 A WDTE bit set, VDD = 4.0V D022* IWDT Watchdog Timer 350 425 A BODEN bit set, VDD = 5.0V D022A* IBOR Brown-out Reset * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached..
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 103
PIC16C63A/65B/73B/74B
14.3 DC Characteristics: PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended) PIC16C63A/65B/73B/74B-20 (Commercial, Industrial, Extended) PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2 Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No.
Sym
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP modes) Input High Voltage I/O ports with TTL buffer
VIL D030 D030A D031 D032 D033
VSS VSS VSS Vss Vss
-
0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD
V V V V V
For entire VDD range 4.5V VDD 5.5V
Note1
VIH D040 D040A
2.0 0.25VDD + 0.8V
-
VDD VDD
V V
4.5V VDD 5.5V For entire VDD range
D041 D042 D042A D043
D060 D061 D063 D070 D080
IIL
with Schmitt Trigger buffer 0.8VDD MCLR 0.8VDD OSC1 (XT, HS and LP modes) 0.7VDD OSC1 (in RC mode) 0.9VDD Input Leakage Current (Notes 2, 3) I/O ports MCLR, RA4/T0CKI OSC1 50 -
-
VDD VDD VDD VDD
V V V V
For entire VDD range Note1
250 -
1 5 5 400 0.6 0.6 0.6 0.6
A A A A V V V V
IPURB VOL
PORTB weak pull-up current Output Low Voltage I/O ports
Vss VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc modes VDD = 5V, VPIN = VSS IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C
D083
OSC2/CLKOUT (RC osc mode)
-
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
*
DS30605A-page 104
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2 Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No. D090
Sym
Characteristic Output High Voltage I/O ports (Note 3)
VOH
VDD-0.7 VDD-0.7
-
8.5
V V V V V
D092
OSC2/CLKOUT (RC osc mode)
VDD-0.7 VDD-0.7
D150*
D100
Open-Drain High Voltage Capacitive Loading Specs on Output Pins COSC2 OSC2 pin
VOD
-
IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101 D102
CIO
All I/O pins and OSC2 (in RC mode)
-
-
50
pF
400 pF Cb SCL, SDA in I2C mode These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. *
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 105
PIC16C63A/65B/73B/74B
14.4
14.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free T Time 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only)
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid Hi-impedance High Low
TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition
SU STO
Setup STOP condition
DS30605A-page 106
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 14-1 apply to all timing specifications unless otherwise noted. Figure 14-1 specifies the load conditions for the timing specifications.
TABLE 14-1:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2. LC parts operate for commercial/industrial temp's only.
AC CHARACTERISTICS
FIGURE 14-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 VDD/2 CL VSS Pin VSS Note1: PORTD and PORTE are not implemented on the PIC16C63A/73B. CL RL = 464 CL = 50 pF 15 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports for OSC2 output Load condition 2
RL
Pin
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 107
PIC16C63A/65B/73B/74B
14.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 14-2: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 2 3 3 4 4
CLKOUT
TABLE 14-2:
Param No. 1A Sym Fosc
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency (Note 1) Min DC DC DC DC Oscillator Frequency (Note 1) DC 0.1 4 5 250 250 50 5 250 250 250 50 5 200 100 2.5 15 -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 4 4 20 200 4 4 20 200 -- -- -- -- -- 10,000 250 250 -- DC -- -- -- 25 50 15 Units Conditions MHz MHz MHz kHz MHz MHz MHz kHz ns ns ns s ns ns ns ns s ns ns s ns ns ns ns RC and XT osc modes HS osc mode (-04) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode RC and XT osc modes HS osc mode (-04) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode (-04) HS osc mode (-20) LP osc mode TCY = 4/FOSC XT oscillator LP oscillator HS oscillator XT oscillator LP oscillator HS oscillator
1
Tosc
External CLKIN Period (Note 1)
Oscillator Period (Note 1)
2 3*
TCY TosL, TosH TosR, TosF *
Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time
4*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note1:
Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30605A-page 108
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 18 12 16 11 Q1 Q2 Q3
20, 21 Note: Refer to Figure 14-1 for load conditions.
TABLE 14-3:
Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* 18A* 19* 20* 20A* 21* 21A* 22* 23* * Tinp Trbp TioF Sym
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Standard Extended (LC) Standard Extended (LC) Port output fall time INT pin high or low time RB7:RB4 change INT high or low time Standard Extended (LC) Min -- -- -- -- -- Tosc + 200 0 -- 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5TCY + 20 -- -- 150 -- -- -- 40 80 40 80 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
TosH2ckL TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR
TosH2ckH OSC1 to CLKOUT
Port input valid to OSC1 (I/O in setup time) Port output rise time
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edge.
Note1:
Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 109
PIC16C63A/65B/73B/74B
FIGURE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins Note: Refer to Figure 14-1 for load conditions. 32 30
31
34
FIGURE 14-5: BROWN-OUT RESET TIMING
BVDD VDD 35
TABLE 14-4:
Parameter No. 30 31* 32 33* 34 35 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ TBOR Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or WDT reset Brown-out Reset Pulse Width Min 2 7 -- 28 -- 100 Typ -- 18 1024 TOSC 72 -- -- Max -- 33 -- 132 2.1 -- Units Conditions
s
ms -- ms
VDD = 5V, -40C to +125C VDD = 5V, -40C to +125C TOSC = OSC1 period VDD = 5V, -40C to +125C
s s
VDD BVDD (D005)
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30605A-page 110
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 42 T1OSO/T1CKI
41
45 47 TMR0 or TMR1
Note: Refer to Figure 14-1 for load conditions.
46 48
TABLE 14-5:
Param No. 40* 41* 42* Sym Tt0H
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 Typ -- -- -- -- -- -- Max -- -- -- -- -- -- Units Conditions ns ns ns ns ns ns Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4,..., 256) Must also meet parameter 47
45*
46*
47*
48
10 Tt0L T0CKI Low Pulse Width 0.5TCY + 20 10 Tt0P T0CKI Period TCY + 40 No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, Standard 15 Prescaler = 25 Extended (LC) 2,4,8 Asynchronous Standard 30 50 Extended (LC) Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, Standard 15 Prescaler = 25 Extended (LC) 2,4,8 Asynchronous Standard 30 50 Extended (LC) Tt1P T1CKI input period Synchronous Standard Greater of: 30 OR TCY + 40 N Extended (LC) Greater of: 50 OR TCY + 40 N Asynchronous Standard 60 100 Extended (LC) Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns
Must also meet parameter 47
N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8)
-- -- -- --
-- -- 200 7Tosc
ns ns kHz --
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 111
PIC16C63A/65B/73B/74B
FIGURE 14-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx (Capture Mode)
50 52
51
CCPx (Compare or PWM Mode) 53 Note: Refer to Figure 14-1 for load conditions. 54
TABLE 14-6:
Param No. 50*
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Min No Prescaler With Prescaler Standard Extended (LC) 0.5TCY + 20 10 20 0.5TCY + 20 Standard Extended (LC) 10 20 3TCY + 40 N Standard Extended (LC) -- -- -- -- Typ Max Units Conditions -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 45 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4, or 16)
Sym Characteristic TccL CCP1 and CCP2 input low time
51*
TccH CCP1 and CCP2 input high time
No Prescaler With Prescaler
52* 53*
TccP CCP1 and CCP2 input period TccR CCP1 and CCP2 output rise time
54*
TccF CCP1 and CCP2 output fall time
Standard Extended (LC)
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30605A-page 112
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-8: PARALLEL SLAVE PORT TIMING (PIC16C65B/74B)
RE2/CS
RE0/RD
RE1/WR
65 RD7:RD0 62 63 Note: Refer to Figure 14-1 for load conditions.
64
TABLE 14-7:
Parameter No. 62* 63*
PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)
Sym Characteristic Min 20 20 35 -- 10 Typ -- -- -- -- -- Max -- -- -- 80 30 Units ns ns ns ns ns Conditions
TdtV2wrH Data in valid before WR or CS (setup time) TwrH2dtI WR or CS to data-in invalid (hold time) RD and CS to data-out valid RD or CS to data-out invalid Standard Extended (LC)
64 65* *
TrdL2dtV TrdH2dtI
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 113
PIC16C63A/65B/73B/74B
FIGURE 14-9: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS 70 SCK (CKP = 0) 71 72
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb IN 74 73 Refer to Figure 14-1 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSb
LSb IN
TABLE 14-8:
Param. No.
70 71 71A 72
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Characteristic Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 100 Typ Max Units -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns Conditions
Symbol
Note 1 Continuous 72A Single Byte Note 1 73 TdiV2scH, Setup time of SDI data input to SCK edge TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 -- -- ns Note 1 edge of Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 -- -- ns TscL2diL 75 TdoR SDO data output rise time Standard -- 10 25 ns Extended (LC) -- 20 45 ns 76 TdoF SDO data output fall time -- 10 25 ns 78 TscR SCK output rise time Standard -- 10 25 ns (master mode) Extended (LC) -- 20 45 ns 79 TscF SCK output fall time (master mode) -- 10 25 ns 80 TscH2doV, SDO data output valid Standard -- -- 50 ns TscL2doV after SCK edge Extended (LC) -- -- 100 ns Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Specification 73A is only required if specifications 71A and 72A are used. TscL SCK input low time (slave mode)
TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time Continuous (slave mode) Single Byte
DS30605A-page 114
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
SDO
MSb 75, 76
BIT6 - - - - - -1
LSb
SDI
MSb IN 74
BIT6 - - - -1
LSb IN
Refer to Figure 14-1 for load conditions.
TABLE 14-9:
Param. No.
71 71A 72 72A 73 73A 74 75 76 78
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Characteristic Continuous Single Byte SCK input low time Continuous (slave mode) Single Byte Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time Standard Extended (LC) SCK input high time (slave mode) Min 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 100 -- Typ Max Units -- -- -- -- -- -- -- 10 20 10 10 20 10 -- -- -- -- -- -- -- -- -- -- 25 45 25 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions
Symbol TscH TscL TdiV2scH, TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TscR
Note 1 Note 1
Note 1
SDO data output fall time -- SCK output rise time Standard -- (master mode) Extended (LC) 79 TscF SCK output fall time (master mode) -- 80 TscH2doV, SDO data output valid Standard -- TscL2doV after SCK edge Extended (LC) 81 TdoV2scH, SDO data output setup to SCK edge TCY TdoV2scL Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Specification 73A is only required if specifications 71A and 72A are used.
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 115
PIC16C63A/65B/73B/74B
FIGURE 14-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS 70 SCK (CKP = 0) 71 72 83
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb IN 74 73 Refer to Figure 14-1 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSb 77 LSb IN
TABLE 14-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param. No.
70 71 71A 72 72A 73 73A 74 75 76 77 78 79 80 83
Symbol
Characteristic
Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 100 -- -- 10 -- -- -- 1.5TCY + 40
Typ Max Units -- -- -- -- -- -- -- -- 10 20 10 -- 10 20 10 -- -- -- -- -- -- -- -- -- -- -- 25 45 25 50 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Conditions
TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time Continuous (slave mode) Single Byte Continuous Single Byte TdiV2scH, Setup time of SDI data input to SCK edge TdiV2scL TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 TscH2diL, Hold time of SDI data input to SCK edge TscL2diL TdoR SDO data output rise time Standard Extended (LC) TdoF SDO data output fall time TssH2doZ SS to SDO output hi-impedance TscR SCK output rise time Standard (master mode) Extended (LC) TscF SCK output fall time (master mode) TscH2doV, SDO data output valid Standard TscL2doV after SCK edge Extended (LC) TscH2ssH, SS after SCK edge TscL2ssH TscL SCK input low time (slave mode)
Note 1 Note 1
Note 1
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note1:
Specification 73A is only required if specifications 71A and 72A are used.
DS30605A-page 116
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82 SS
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
BIT6 - - - - - -1
LSb 77
SDI
MSb IN
BIT6 - - - -1
LSb IN
74 Refer to Figure 14-1 for load conditions.
TABLE 14-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param. No.
70 71 71A 72 72A 73A 74 75 76 77 78 79 80 82 83
Symbol TssL2scH, TssL2scL TscH TscL TB2B TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR
Characteristic SS to SCK or SCK input SCK input high time (slave mode) Continuous Single Byte SCK input low time Continuous (slave mode) Single Byte Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time Standard Extended (LC)
Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 1.5TCY + 40 100 -- -- 10 -- -- -- -- -- -- -- 1.5TCY + 40
Typ Max Units -- -- -- -- -- -- -- 10 20 10 -- 10 20 10 -- -- -- -- -- -- -- -- -- -- -- -- 25 45 25 50 25 45 25 50 100 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Conditions
Note 1 Note 1 Note 1
SDO data output fall time SS to SDO output hi-impedance SCK output rise time Standard (master mode) Extended (LC) TscF SCK output fall time (master mode) TscH2doV, SDO data output valid Standard TscL2doV after SCK edge Extended (LC) TssL2doV SDO data output valid Standard after SS edge Extended (LC) TscH2ssH, SS after SCK edge TscL2ssH
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note1:
Specification 73A is only required if specifications 71A and 72A are used.
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 117
PIC16C63A/65B/73B/74B
FIGURE 14-13: I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition Note: Refer to Figure 14-1 for load conditions.
STOP Condition
TABLE 14-12: I2C BUS START/STOP BITS REQUIREMENTS
Parameter No. 90* 91* 92* 93 * Sym TSU:STA THD:STA TSU:STO THD:STO Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units Conditions Only relevant for repeated START condition After this period the first clock pulse is generated
ns ns ns ns
These parameters are characterized but not tested.
DS30605A-page 118
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-14: I2C BUS DATA TIMING
103 100 101 102
SCL
90 91 106 107 92
SDA In
110 109 109
SDA Out Note: Refer to Figure 14-1 for load conditions.
TABLE 14-13: I2C BUS DATA REQUIREMENTS
Parameter No. 100* Sym THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 100 kHz mode 400 kHz mode SSP Module 100 kHz mode 400 kHz mode Min 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1Cb -- 20 + 0.1Cb 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 Units s s Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
101*
TLOW
Clock low time
s s
102*
TR
SDA and SCL rise time
ns ns ns ns s s s s ns s ns ns s s ns ns s s pF
Cb is specified to be from 10-400 pF Cb is specified to be from 10-400 pF Only relevant for repeated START condition After this period the first clock pulse is generated
103*
TF
SDA and SCL fall time 100 kHz mode 400 kHz mode START condition setup time START condition hold time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
90* 91* 106* 107* 92* 109* 110*
TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
Note 2
Note 1 Time the bus must be free before a new transmission can start
*
Cb Bus capacitive loading These parameters are characterized but not tested.
Note1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 119
PIC16C63A/65B/73B/74B
FIGURE 14-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK pin RC7/RX/DT pin 120
121
121
122
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param No. 120* 121* 122* * Sym TckH2dtV Tckrf Tdtrf Characteristic SYNC XMIT (MASTER & SLAVE) Standard Clock high to data out valid Extended (LC) Clock out rise time and fall time (Master Mode) Data out rise time and fall time Standard Extended (LC) Standard Extended (LC) Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 80 100 45 50 45 50 Units ns ns ns ns ns ns Conditions
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 14-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK pin RC7/RX/DT pin
125
126
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter No. 125* 126* * Sym TdtV2ckL TckL2dtl Characteristic SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) Data hold after CK (DT hold time) Min Typ Max Units Conditions
15 15
-- --
-- --
ns ns
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30605A-page 120
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 14-16: A/D CONVERTER CHARACTERISTICS: PIC16C73B/74B-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C73B/74B-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC73B/74B-04 (COMMERCIAL, INDUSTRIAL)
Param Sym Characteristic No. A01 A02 A03 A04 A05 A06 A10 A20 A25 A30 A40 NR Resolution Min -- -- -- -- -- -- -- 2.5V VSS - 0.3 -- -- -- 10 Typ -- -- -- -- -- -- guaranteed -- -- -- 180 90 -- Max 8-bits <1 <1 <1 <1 <1 -- VDD + 0.3 VREF + 0.3 10.0 -- -- 1000 Units bit Conditions VREF = VDD = 5.12V, VSS VAIN VREF
EABS Total Absolute error EIL Integral linearity error
LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF -- V V k A A A Average current consumption when A/D is on. (Note 1) During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 10.1. During A/D Conversion cycle VSS VAIN VREF
EDL Differential linearity error EFS Full scale error EOFF Offset error -- Monotonicity
VREF Reference voltage VAIN Analog input voltage ZAIN Recommended impedance of analog voltage source IAD A/D conversion current (VDD) Standard Extended (LC)
A50
IREF VREF input current (Note 2)
-- *
--
10
A
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note1:
When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
(c) 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 121
PIC16C63A/65B/73B/74B
FIGURE 14-17: A/D CONVERSION TIMING
BSF ADCON0, GO 134 Q4 130 A/D CLK 132 (TOSC/2) (1) 131
1 Tcy
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
SAMPLE
Note1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 14-17: A/D CONVERSION REQUIREMENTS
Param No. 130 Sym Characteristic TAD A/D clock period Standard Extended (LC) Standard Extended (LC) 131 132 TCNV Conversion time (not including S/H time) (Note 1) TACQ Acquisition time Min 1.6 2.0 2.0 3.0 11 Note 2 5* Typ -- -- 4.0 6.0 -- 20 -- Max -- -- 6.0 9.0 11 -- -- Units s s s s TAD s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 3.0V TOSC based, VREF full range A/D RC Mode A/D RC Mode
134
TGO
Q4 to A/D clock start
--
TOSC/2
--
--
135 *
TSWC Switching from convert sample time
1.5
--
--
TAD
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design.
Note1:
ADRES register may be read on the following TCY cycle.
2: See Section 10.1 for min conditions.
DS30605A-page 122
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Graphs and Tables not available at this time.
(c) 1998 Microchip Technology Inc.
DS30605A-page 123
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 124
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.0
16.1
PACKAGING INFORMATION
Package Marking Information 28-Lead PDIP (Skinny DIP) MMMMMMMMMMMM XXXXXXXXXXXXXXX AABBCDE Example PIC16C73B-04/SP 9817HAT
28-Lead CERDIP Windowed XXXXXXXXXXX XXXXXXXXXXX AABBCDE
Example PIC16C73B/JW 9817CAT
28-Lead SOIC MMMMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXXXX AABBCDE
Example PIC16C73B-20/SO 9810/SAA
28-Lead SSOP
XXXXXXXXXXXX XXXXXXXXXXXX
Example
PIC16C73B 20I/SS025
AABBCAE
9817SBP
Microchip part number & customer specific information* Year code (last two digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. - 6" H = Tempe, Arizona, U.S.A. - 8" D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev# and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
Legend: XX...X AA BB C
(c) 1998 Microchip Technology Inc.
DS30605A-page 125
PIC16C63A/65B/73B/74B
Package Marking Information (Cont'd)
40-Lead PDIP MMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXX AABBCDE
Example PIC16C74B-04/P 9812SAA
40-Lead CERDIP Windowed
Example
MMMMMMMMM XXXXXXXXXXX XXXXXXXXXXX AABBCDE
PIC16C74B/JW 9805HAT
Microchip part number & customer specific information* Year code (last two digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. - 6" H = Tempe, Arizona, U.S.A. - 8" D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev# and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
Legend: XX...X AA BB C
DS30605A-page 126
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Package Marking Information (Cont'd) 44-Lead TQFP MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE
Example PIC16C74B -20/PT 9811HAT
44-Lead MQFP MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE
Example PIC16C74B -20/PQ 9804SAT
44-Lead PLCC
Example
MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE
PIC16C74B -20/L 9803SAT
Microchip part number & customer specific information* Year code (last two digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. - 6" H = Tempe, Arizona, U.S.A. - 8" D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev# and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
Legend: XX...X AA BB C
(c) 1998 Microchip Technology Inc.
DS30605A-page 127
PIC16C63A/65B/73B/74B
16.2 K04-070 28-Lead Skinny Plastic Dual In-line (SP) - 300 mil
E
D
2 n E1 A R eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter.
1
A1
c A2 B1 B INCHES* NOM 0.300 28 0.100 0.019 0.016 0.053 0.040 0.005 0.000 0.010 0.008 0.150 0.140 0.090 0.070 0.020 0.015 0.130 0.125 1.365 1.345 0.288 0.280 0.270 0.283 0.320 0.350 5 10 5 10 p
L
MIN n p B B1 R c A A1 A2 L D E E1 eB
MAX
MIN
0.022 0.065 0.010 0.012 0.160 0.110 0.025 0.135 1.385 0.295 0.295 0.380 15 15
MILLIMETERS NOM MAX 7.62 28 2.54 0.41 0.56 0.48 1.02 1.65 1.33 0.00 0.25 0.13 0.20 0.30 0.25 3.56 4.06 3.81 1.78 2.79 2.29 0.38 0.64 0.51 3.18 3.43 3.30 34.16 35.18 34.67 7.11 7.30 7.49 7.49 6.86 7.18 8.13 8.89 9.65 5 10 15 5 10 15
Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS30605A-page 128
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.3 K04-080 28-Lead Ceramic Dual In-line with Window (JW) - 300 mil
E
W2
D
2 n W1 E1 A R eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Radius to Radius Width Overall Row Spacing Window Width Window Length * Controlling Parameter. c A2 INCHES* NOM 0.300 28 0.100 0.019 0.058 0.013 0.010 0.183 0.125 0.023 0.140 1.458 0.290 0.270 0.385 0.140 0.300 B1 B MIN n p B B1 R c A A1 A2 L D E E1 eB W1 W2 MAX p MILLIMETERS NOM MAX MIN 7.62 28 2.54 2.59 2.49 0.47 0.53 0.41 1.46 1.65 1.27 0.32 0.38 0.25 0.25 0.30 0.20 4.32 4.64 4.95 3.18 3.63 2.72 0.76 0.00 0.57 3.43 3.56 3.68 36.32 37.02 37.72 7.24 7.37 7.49 6.48 6.86 7.24 8.76 9.78 10.80 0.13 0.14 0.15 0.29 0.3 0.31 A1 L 1
0.098 0.016 0.050 0.010 0.008 0.170 0.107 0.015 0.135 1.430 0.285 0.255 0.345 0.130 0.290
0.102 0.021 0.065 0.015 0.012 0.195 0.143 0.030 0.145 1.485 0.295 0.285 0.425 0.150 0.310
(c) 1998 Microchip Technology Inc.
DS30605A-page 129
PIC16C63A/65B/73B/74B
16.4 K04-052 28-Lead Plastic Small Outline (SO) - Wide, 300 mil
E1 E p
D
B n X 45 c A L1 A2 INCHES* NOM 0.050 28 0.099 0.093 0.048 0.058 0.004 0.008 0.700 0.706 0.292 0.296 0.394 0.407 0.010 0.020 0.005 0.005 0.005 0.005 0.011 0.016 4 0 0.010 0.015 0.009 0.011 0.014 0.017 0 12 12 0 MILLIMETERS NOM MAX 1.27 28 2.36 2.64 2.50 1.22 1.73 1.47 0.10 0.28 0.19 17.78 18.08 17.93 7.42 7.51 7.59 10.64 10.01 10.33 0.50 0.25 0.74 0.13 0.13 0.25 0.13 0.25 0.13 0.53 0.41 0.28 0 4 8 0.38 0.51 0.25 0.27 0.30 0.23 0.36 0.42 0.48 0 12 15 0 12 15 A1 L R2 2 1
Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
R1
MIN p n A A1 A2 D E E1 X R1 R2 L L1 c B
MAX
MIN
0.104 0.068 0.011 0.712 0.299 0.419 0.029 0.010 0.010 0.021 8 0.020 0.012 0.019 15 15
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS30605A-page 130
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.5 K04-073 28-Lead Plastic Shrink Small Outline (SS) - 5.30 mm
E1 E p
D
B n 2 1 L c R2 A
A1 R1 L1 A2
Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
MIN p n A A1 A2 D E E1 R1 R2 L L1 c B
INCHES NOM 0.026 28 0.073 0.068 0.036 0.026 0.005 0.002 0.396 0.402 0.205 0.208 0.301 0.306 0.005 0.005 0.005 0.005 0.015 0.020 0 4 0.000 0.005 0.005 0.007 0.010 0.012 0 5 0 5
MAX
MIN
0.078 0.046 0.008 0.407 0.212 0.311 0.010 0.010 0.025 8 0.010 0.009 0.015 10 10
MILLIMETERS* NOM MAX 0.65 28 1.99 1.73 1.86 1.17 0.66 0.91 0.21 0.05 0.13 10.33 10.07 10.20 5.38 5.20 5.29 7.90 7.65 7.78 0.25 0.13 0.13 0.25 0.13 0.13 0.64 0.38 0.51 0 4 8 0.25 0.00 0.13 0.22 0.13 0.18 0.38 0.25 0.32 10 0 5 10 0 5
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
(c) 1998 Microchip Technology Inc.
DS30605A-page 131
PIC16C63A/65B/73B/74B
16.6 K04-016 40-Lead Plastic Dual In-line (P) - 600 mil
E
D
n E1
2 1
A1 A
R eB
c B1 A2 INCHES* NOM 0.600 40 0.100 0.018 0.016 0.050 0.045 0.005 0.000 0.010 0.009 0.160 0.110 0.073 0.093 0.020 0.020 0.125 0.130 2.013 2.018 0.530 0.535 0.545 0.565 0.630 0.610 5 10 5 10 B p
L
Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter.
MIN n p B B1 R c A A1 A2 L D E E1 eB
MAX
MIN
0.020 0.055 0.010 0.011 0.160 0.113 0.040 0.135 2.023 0.540 0.585 0.670 15 15
MILLIMETERS MAX NOM 15.24 40 2.54 0.51 0.46 0.41 1.40 1.27 1.14 0.25 0.13 0.00 0.28 0.25 0.23 4.06 4.06 2.79 2.36 1.85 2.87 0.51 0.51 1.02 3.18 3.30 3.43 51.13 51.26 51.38 13.46 13.59 13.72 14.35 14.86 13.84 15.49 17.02 16.00 5 10 15 5 10 15
Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS30605A-page 132
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.7 K04-014 40-Lead Ceramic Dual In-line with Window (JW) - 600 mil
E
W
D
n E1
2 1 A1 A R eB A2 c B1 B p L
Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Radius to Radius Width Overall Row Spacing Window Diameter
*
MIN n p B B1 R c A A1 A2 L D E E1 eB W
0.098 0.016 0.050 0.000 0.008 0.190 0.117 0.030 0.135 2.040 0.514 0.560 0.610 0.340
INCHES* NOM 0.600 40 0.100 0.020 0.053 0.005 0.011 0.205 0.135 0.045 0.140 2.050 0.520 0.580 0.660 0.350
MAX
MIN
0.102 0.023 0.055 0.010 0.014 0.220 0.153 0.060 0.145 2.060 0.526 0.600 0.710 0.360
MILLIMETERS MAX NOM 15.24 40 2.59 2.49 2.54 0.58 0.41 0.50 1.40 1.27 1.33 0.25 0.00 0.13 0.36 0.20 0.28 5.59 4.83 5.21 3.89 2.97 3.43 1.52 0.00 1.14 3.68 3.43 3.56 52.32 51.82 52.07 13.36 13.06 13.21 15.24 14.22 14.73 18.03 15.49 16.76 9.14 8.64 8.89
Controlling Parameter.
(c) 1998 Microchip Technology Inc.
DS30605A-page 133
PIC16C63A/65B/73B/74B
16.8 K04-076 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form
E1 E # leads = n1 p
D
D1
B n
2 1
X x 45 L R2 c L1 A
Units Dimension Limits Pitch Number of Pins Pins along Width Overall Pack. Height Shoulder Height Standoff Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Outside Tip Length Outside Tip Width Molded Pack. Length Molded Pack. Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom
*
R1
A2 INCHES NOM 0.031 44 11 0.043 0.025 0.004 0.003 0.006 0.010 3.5 0.008 0.006 0.015 0.472 0.472 0.394 0.394 0.035 10 12
A1
MIN p n n1 A A1 A2 R1 R2 L L1 c B D1 E1 D E X
MAX
MIN
0.039 0.015 0.002 0.003 0.003 0.005 0 0.003 0.004 0.012 0.463 0.463 0.390 0.390 0.025 5 5
0.047 0.035 0.006 0.010 0.008 0.015 7 0.013 0.008 0.018 0.482 0.482 0.398 0.398 0.045 15 15
MILLIMETERS* NOM MAX 0.80 44 11 1.20 1.00 1.10 0.89 0.38 0.64 0.15 0.05 0.10 0.25 0.08 0.08 0.20 0.08 0.14 0.38 0.13 0.25 7 0 3.5 0.33 0.08 0.20 0.20 0.09 0.15 0.45 0.30 0.38 12.25 11.75 12.00 12.25 11.75 12.00 9.90 10.00 10.10 9.90 10.00 10.10 0.64 0.89 1.14 5 10 15 5 12 15
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B."
Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E." JEDEC equivalent: MS-026 ACB
DS30605A-page 134
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.9 K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form
E1 E # leads = n1 p
D D1
2 1 B n
X x 45 L R2
c R1 L1
A
Units Dimension Limits Pitch Number of Pins Pins along Width Overall Pack. Height Shoulder Height Standoff Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Outside Tip Length Outside Tip Width Molded Pack. Length Molded Pack. Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom
*
A2
A1 MILLIMETERS* NOM MAX 0.80 44 11 2.35 2.18 2.00 1.41 1.11 0.81 0.25 0.15 0.05 0.25 0.13 0.13 0.38 0.13 0.30 0.64 0.38 0.51 7 0 3.5 0.53 0.28 0.41 0.23 0.13 0.18 0.45 0.30 0.37 13.45 13.20 12.95 13.45 13.20 12.95 9.90 10.00 10.10 9.90 10.00 10.10 0.89 1.143 0.635 5 10 15 5 12 15
MIN p n n1 A A1 A2 R1 R2 L L1 c B D1 E1 D E X
0.079 0.032 0.002 0.005 0.005 0.015 0 0.011 0.005 0.012 0.510 0.510 0.390 0.390 0.025 5 5
INCHES NOM 0.031 44 11 0.086 0.044 0.006 0.005 0.012 0.020 3.5 0.016 0.007 0.015 0.520 0.520 0.394 0.394 0.035 10 12
MAX
MIN
0.093 0.056 0.010 0.010 0.015 0.025 7 0.021 0.009 0.018 0.530 0.530 0.398 0.398 0.045 15 15
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B."
Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E." JEDEC equivalent: MS-022 AB
(c) 1998 Microchip Technology Inc.
DS30605A-page 135
PIC16C63A/65B/73B/74B
16.10 K04-048 44-Lead Plastic Leaded Chip Carrier (L) - Square
E1 E # leads = n1
D D1
n12 CH2 x 45 R1 A1 c R2 E2 Units Dimension Limits Number of Pins Pitch Overall Pack. Height Shoulder Height Standoff Side 1 Chamfer Dim. Corner Chamfer (1) Corner Chamfer (other) Overall Pack. Width Overall Pack. Length Molded Pack. Width Molded Pack. Length Footprint Width Footprint Length Pins along Width Lead Thickness Upper Lead Width Lower Lead Width Upper Lead Length Shoulder Inside Radius J-Bend Inside Radius Mold Draft Angle Top Mold Draft Angle Bottom
*
CH1 x 45 A
A3
L
35
A2
B1 B p D2
MIN n p A A1 A2 A3 CH1 CH2 E1 D1 E D E2 D2 n1 c B1 B L R1 R2
0.165 0.095 0.015 0.024 0.040 0.000 0.685 0.685 0.650 0.650 0.610 0.610 0.008 0.026 0.015 0.050 0.003 0.015 0 0
INCHES* NOM 44 0.050 0.173 0.103 0.023 0.029 0.045 0.005 0.690 0.690 0.653 0.653 0.620 0.620 11 0.010 0.029 0.018 0.058 0.005 0.025 5 5
MAX
MIN
0.180 0.110 0.030 0.034 0.050 0.010 0.695 0.695 0.656 0.656 0.630 0.630 0.012 0.032 0.021 0.065 0.010 0.035 10 10
MILLIMETERS NOM MAX 44 1.27 4.57 4.19 4.38 2.79 2.41 2.60 0.76 0.38 0.57 0.86 0.61 0.74 1.27 1.02 1.14 0.25 0.00 0.13 17.65 17.53 17.40 17.65 17.40 17.53 16.66 16.51 16.59 16.66 16.51 16.59 16.00 15.75 15.49 16.00 15.75 15.49 11 0.30 0.25 0.20 0.81 0.66 0.74 0.38 0.53 0.46 1.65 1.27 1.46 0.08 0.25 0.13 0.38 0.89 0.64 5 10 0 0 5 10
Controlling Parameter. Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1."
Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E." JEDEC equivalent: MO-047 AC
DS30605A-page 136
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
APPENDIX A: REVISION HISTORY
Version A Date 7/98 Revision Description This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234D, and the PIC16C7X Data Sheet, DS30390E.
APPENDIX B: DEVICE DIFFERENCES
The differences between the devices in this data sheet are listed in Table B-1.
TABLE B-1: Difference
A/D
DEVICE DIFFERENCES PIC16C63A
no no 28-pin PDIP, 28-pin windowed CERDIP, 28-pin SOIC, 28-pin SSOP no yes 40-pin PDIP, 40-pin windowed CERDIP, 44-pin TQFP, 44-pin MQFP, 44-pin PLCC
PIC16C65B
PIC16C73B
5 channels, 8 bits no 28-pin PDIP, 28-pin windowed CERDIP, 28-pin SOIC, 28-pin SSOP
PIC16C74B
8 channels, 8 bits yes 40-pin PDIP, 40-pin windowed CERDIP, 44-pin TQFP, 44-pin MQFP, 44-pin PLCC
Parallel Slave Port Packages
APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS PIC16C63/65A/73A/74A
2.5V - 6.0V single mode SPI Can only transmit one word in SPI mode of enhanced SSP. CCP does not reset TMR1 when in special event trigger mode. USART receiver errata in BRGH=1 mode. Writing to TMR1L register can cause overflow in TMR1H register.
Difference
Voltage Range SSP module SSP module CCP module USART module Timer1 module
PIC16C63A/65B/73B/74B
2.5V - 5.5V 4-mode SPI N/A N/A N/A N/A
(c) 1998 Microchip Technology Inc.
DS30605A-page 137
PIC16C63A/65B/73B/74B
APPENDIX D: MIGRATION FROM BASELINE TO MIDRANGE DEVICES
This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to a midrange device (i.e., PIC16CXXX). The following are the list of modifications over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. Bits PA2, PA1, PA0 are removed from STATUS register. Data memory paging is redefined slightly. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change feature. T0CKI pin is also a port pin (RA4) now. FSR is made a full eight bit register. "In-circuit serial programming" is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). PCON status register is added with a Power-on Reset status bit (POR). Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. 18. Brown-out protection circuitry has been added. Controlled by configuration word bit BODEN. Brown-out reset ensures the device is placed in a reset condition if VDD dips below a fixed setpoint. To convert code written for PIC16C5X to PIC16CXXX, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h.
3. 4. 5.
2.
3. 4.
5. 6. 7. 8. 9.
10. 11.
12. 13. 14. 15.
16. 17.
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APPENDIX E: BIT/REGISTER CROSSREFERENCE LIST
ADCS1:ADCS0 ..................................ADCON0<7:6> ADIE ...................................................PIE1<6> ADIF ...................................................PIR1<6> ADON .................................................ADCON0<0> BF ......................................................SSPSTAT<0> BOR ...................................................PCON<0> BRGH .................................................TXSTA<2> C ........................................................STATUS<0> CCP1IE ..............................................PIE1<2> CCP1IF ..............................................PIR1<2> CCP1M3:CCP1M0 .............................CCP1CON<3:0> CCP1X:CCP1Y ..................................CCP1CON<5:4> CCP2IE ..............................................PIE2<0> CCP2IF ..............................................PIR2<0> CCP2M3:CCP2M0 .............................CCP2CON<3:0> CCP2X:CCP2Y ..................................CCP2CON<5:4> CHS2:CHS0 .......................................ADCON0<5:3> CKE ....................................................SSPSTAT<6> CKP ....................................................SSPCON<4> CREN .................................................RCSTA<4> CSRC .................................................TXSTA<7> D/A .....................................................SSPSTAT<5> DC ......................................................STATUS<1> FERR .................................................RCSTA<2> GIE .....................................................INTCON<7> GO/DONE ..........................................ADCON0<2> IBF .....................................................TRISE<7> IBOV ...................................................TRISE<5> INTE ...................................................INTCON<4> INTEDG .............................................OPTION_REG<6> INTF ...................................................INTCON<1> IRP .....................................................STATUS<7> OBF ....................................................TRISE<6> OERR .................................................RCSTA<1> P .........................................................SSPSTAT<4> PCFG2:PCFG0 ..................................ADCON1<2:0> PD ......................................................STATUS<3> PEIE ...................................................INTCON<6> POR ...................................................PCON<1> PS2:PS0 ............................................OPTION_REG<2:0> PSA ....................................................OPTION_REG<3> PSPIE ................................................PIE1<7> PSPIF .................................................PIR1<7> PSPMODE .........................................TRISE<4> R/W ....................................................SSPSTAT<2> RBIE ...................................................INTCON<3> RBIF ...................................................INTCON<0> RBPU .................................................OPTION_REG<7> RCIE ..................................................PIE1<5> RCIF ...................................................PIR1<5> RP1:RP0 ............................................STATUS<6:5> RX9 ....................................................RCSTA<6> RX9D .................................................RCSTA<0> S .........................................................SSPSTAT<3> SMP ...................................................SSPSTAT<7> SPEN .................................................RCSTA<7> SREN .................................................RCSTA<5> SSPEN ...............................................SSPCON<5> SSPIE ................................................PIE1<3> SSPIF .................................................PIR1<3> SSPM3:SSPM0 ..................................SSPCON<3:0> SSPOV ...............................................SSPCON<6> SYNC .................................................TXSTA<4> T0CS ..................................................OPTION_REG<5> T0IE ................................................... INTCON<5> T0IF ................................................... INTCON<2> T0SE .................................................. OPTION_REG<4> T1CKPS1:T1CKPS0 .......................... T1CON<5:4> T1OSCEN .......................................... T1CON<3> T1SYNC ............................................ T1CON<2> T2CKPS1:T2CKPS0 .......................... T2CON<1:0> TMR1CS ............................................ T1CON<1> TMR1IE ............................................. PIE1<0> TMR1IF .............................................. PIR1<0> TMR1ON ........................................... T1CON<0> TMR2IE ............................................. PIE1<1> TMR2IF .............................................. PIR1<1> TMR2ON ........................................... T2CON<2> TO ...................................................... STATUS<4> TOUTPS3:TOUTPS0 ......................... T2CON<6:3> TRMT ................................................. TXSTA<1> TX9 .................................................... TXSTA<6> TX9D ................................................. TXSTA<0> TXEN ................................................. TXSTA<5> TXIE ................................................... PIE1<4> TXIF ................................................... PIR1<4> UA ...................................................... SSPSTAT<1> WCOL ................................................ SSPCON<7> Z ........................................................ STATUS<2>
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NOTES:
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INDEX
A
A/D ...................................................................................... 75 A/D Converter Enable (ADIE Bit) ................................ 18 A/D Converter Flag (ADIF Bit) .............................. 19, 77 A/D Converter Interrupt, Configuring .......................... 77 ADCON0 Register................................................. 13, 75 ADCON1 Register........................................... 14, 75, 76 ADRES Register ............................................. 13, 75, 77 Analog Port Pins ....................................... 7, 8, 9, 34, 35 Analog Port Pins, Configuring..................................... 79 Block Diagram............................................................. 77 Block Diagram, Analog Input Model............................ 78 Channel Select (CHS2:CHS0 Bits) ............................. 75 Clock Select (ADCS1:ADCS0 Bits)............................. 75 Configuring the Module............................................... 77 Conversion Clock (TAD) .............................................. 79 Conversion Status (GO/DONE Bit) ....................... 75, 77 Conversions ................................................................ 80 Converter Characteristics ......................................... 121 Module On/Off (ADON Bit).......................................... 75 Port Configuration Control (PCFG2:PCFG0 Bits) ....... 76 Sampling Requirements.............................................. 78 Special Event Trigger (CCP)................................. 47, 80 Timing Diagram......................................................... 122 Absolute Maximum Ratings .............................................. 101 ADCON0 Register......................................................... 13, 75 ADCS1:ADCS0 Bits .................................................... 75 ADON Bit .................................................................... 75 CHS2:CHS0 Bits......................................................... 75 GO/DONE Bit........................................................ 75, 77 ADCON1 Register................................................... 14, 75, 76 PCFG2:PCFG0 Bits .................................................... 76 ADRES Register ..................................................... 13, 75, 77 Architecture PIC16C63A/PIC16C73B Block Diagram....................... 5 PIC16C65B/PIC16C74B Block Diagram....................... 6 Assembler MPASM Assembler..................................................... 98 Flag (CCP2IF Bit) ............................................... 21 RC1/T1OSI/CCP2 Pin ...................................... 7, 9 Interaction of Two CCP Modules................................ 45 Timer Resources ........................................................ 45 Timing Diagram ........................................................ 112 CCP1CON Register............................................................ 45 CCP1M3:CCP1M0 Bits .............................................. 45 CCP1X:CCP1Y Bits.................................................... 45 CCP2CON Register............................................................ 45 CCP2M3:CCP2M0 Bits .............................................. 45 CCP2X:CCP2Y Bits.................................................... 45 Code Protection ............................................................ 81, 94 CP1:CP0 Bits.............................................................. 81 Compare (CCP Module) ..................................................... 47 Block Diagram ............................................................ 47 CCP Pin Configuration ............................................... 47 CCPR1H:CCPR1L Registers ..................................... 47 Software Interrupt ....................................................... 47 Special Event Trigger ..................................... 41, 47, 80 Timer1 Mode Selection............................................... 47 Configuration Bits ............................................................... 81 Conversion Considerations .............................................. 137
D
Data Memory ...................................................................... 11 Bank Select (RP1:RP0 Bits) ................................. 11, 15 General Purpose Registers ........................................ 11 Register File Map ....................................................... 12 Special Function Registers................................... 12, 13 DC Characteristics.................................................... 102, 104 Development Support ......................................................... 97 Development Tools............................................................. 97 Device Differences ........................................................... 137 Direct Addressing ............................................................... 24
E
Electrical Characteristics .................................................. 101 Errata .....................................................................................4 External Power-on Reset Circuit ........................................ 85
F
Firmware Instructions ......................................................... 95 ftp site ............................................................................... 147 Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) .................... 99
B
Banking, Data Memory ................................................. 11, 15 Brown-out Reset (BOR) .............................. 81, 83, 85, 86, 87 BOR Enable (BODEN Bit)........................................... 81 BOR Status (BOR Bit)................................................. 22 Timing Diagram......................................................... 110
I
I/O Ports ............................................................................. 25 I2C (SSP Module) ............................................................... 56 ACK Pulse .......................................... 56, 57, 58, 59, 60 Addressing.................................................................. 57 Block Diagram ............................................................ 56 Buffer Full Status (BF Bit)........................................... 52 Clock Polarity Select (CKP Bit)................................... 53 Data/Address (D/A Bit) ............................................... 52 Master Mode............................................................... 60 Mode Select (SSPM3:SSPM0 Bits)............................ 53 Multi-Master Mode...................................................... 60 Read/Write Bit Information (R/W Bit)........ 52, 57, 58, 59 Receive Overflow Indicator (SSPOV Bit).................... 53 Reception ................................................................... 58 Reception Timing Diagram ......................................... 58 Serial Clock (RC3/SCK/SCL) ..................................... 59 Slave Mode................................................................. 56 Start (S Bit) ........................................................... 52, 60 Stop (P Bit) ........................................................... 52, 60 Synchronous Serial Port Enable (SSPEN Bit)............ 53 Timing Diagram, Data............................................... 119 Timing Diagram, Start/Stop Bits ............................... 118 Transmission .............................................................. 59 Update Address (UA Bit) ............................................ 52 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 97
C
Capture (CCP Module) ....................................................... 46 Block Diagram............................................................. 46 CCP Pin Configuration................................................ 46 CCPR1H:CCPR1L Registers...................................... 46 Changing Between Capture Prescalers...................... 46 Software Interrupt ....................................................... 46 Timer1 Mode Selection ............................................... 46 Capture/Compare/PWM (CCP)........................................... 45 CCP1 .......................................................................... 45 CCP1CON Register ...................................... 13, 45 CCPR1H Register......................................... 13, 45 CCPR1L Register ......................................... 13, 45 Enable (CCP1IE Bit) ........................................... 18 Flag (CCP1IF Bit) ............................................... 19 RC2/CCP1 Pin.................................................. 7, 9 CCP2 .......................................................................... 45 CCP2CON Register ...................................... 13, 45 CCPR2H Register......................................... 13, 45 CCPR2L Register ......................................... 13, 45 Enable (CCP2IE Bit) ........................................... 20
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ID Locations .................................................................. 81, 94 In-Circuit Serial Programming (ICSP) ........................... 81, 94 Indirect Addressing ............................................................. 24 FSR Register .................................................. 11, 13, 24 INDF Register ............................................................. 13 Instruction Format ............................................................... 95 Instruction Set ..................................................................... 95 Summary Table........................................................... 96 INTCON Register .......................................................... 13, 17 GIE Bit......................................................................... 17 INTE Bit....................................................................... 17 INTF Bit ....................................................................... 17 PEIE Bit....................................................................... 17 RBIE Bit ...................................................................... 17 RBIF Bit................................................................. 17, 27 T0IE Bit ....................................................................... 17 T0IF Bit ....................................................................... 17 Interrupt Sources........................................................... 81, 90 A/D Conversion Complete .......................................... 77 Block Diagram............................................................. 90 Capture Complete (CCP)............................................ 46 Compare Complete (CCP).......................................... 47 Interrupt on Change (RB7:RB4 )................................. 27 RB0/INT Pin, External......................................... 7, 8, 91 SSP Receive/Transmit Complete ............................... 51 TMR0 Overflow ..................................................... 38, 91 TMR1 Overflow ..................................................... 39, 41 TMR2 to PR2 Match ................................................... 44 TMR2 to PR2 Match (PWM) ................................. 43, 48 USART Receive/Transmit Complete .......................... 61 Interrupts, Context Saving During ....................................... 91 Interrupts, Enable Bits A/D Converter Enable (ADIE Bit) ................................ 18 CCP1 Enable (CCP1IE Bit)................................... 18, 46 CCP2 Enable (CCP2IE Bit)......................................... 20 Global Interrupt Enable (GIE Bit) .......................... 17, 90 Interrupt on Change (RB7:RB4) Enable (RBIE Bit) .............................................................. 17, 91 Peripheral Interrupt Enable (PEIE Bit) ........................ 17 PSP Read/Write Enable (PSPIE Bit) .......................... 18 RB0/INT Enable (INTE Bit) ......................................... 17 SSP Enable (SSPIE Bit) ............................................. 18 TMR0 Overflow Enable (T0IE Bit)............................... 17 TMR1 Overflow Enable (TMR1IE Bit) ......................... 18 TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 18 USART Receive Enable (RCIE Bit) ............................ 18 USART Transmit Enable (TXIE Bit) ............................ 18 Interrupts, Flag Bits A/D Converter Flag (ADIF Bit) .............................. 19, 77 CCP1 Flag (CCP1IF Bit) ................................. 19, 46, 47 CCP2 Flag (CCP2IF Bit) ............................................. 21 Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ........................................................ 17, 27, 91 PSP Read/Write Flag (PSPIF Bit)............................... 19 RB0/INT Flag (INTF Bit).............................................. 17 SSP Flag (SSPIF Bit).................................................. 19 TMR0 Overflow Flag (T0IF Bit) ............................. 17, 91 TMR1 Overflow Flag (TMR1IF Bit) ............................. 19 TMR2 to PR2 Match Flag (TMR2IF Bit) ...................... 19 USART Receive Flag (RCIF Bit) ................................. 19 USART Transmit Flag (TXIE Bit) ................................ 19 Memory Organization Data Memory .............................................................. 11 Program Memory ........................................................ 11 MP-DriveWayTM - Application Code Generator .................. 99 MPLAB C ............................................................................ 99 MPLAB Integrated Development Environment Software ..................................................................... 98
O
On-Line Support ............................................................... 147 OPCODE Field Descriptions............................................... 95 OPTION_REG Register................................................ 14, 16 INTEDG Bit ................................................................. 16 PS2:PS0 Bits ........................................................ 16, 37 PSA Bit ................................................................. 16, 37 RBPU Bit .................................................................... 16 T0CS Bit ............................................................... 16, 37 T0SE Bit ............................................................... 16, 37 OSC1/CLKIN Pin .............................................................. 7, 8 OSC2/CLKOUT Pin .......................................................... 7, 8 Oscillator Configuration ................................................ 81, 82 HS......................................................................... 82, 86 LP ......................................................................... 82, 86 RC .................................................................. 82, 83, 86 Selection (FOSC1:FOSC0 Bits) ................................. 81 XT ......................................................................... 82, 86 Oscillator, Timer1.......................................................... 39, 41 Oscillator, WDT................................................................... 92
P
Packaging ......................................................................... 125 Paging, Program Memory............................................. 11, 23 Parallel Slave Port (PSP).......................................... 9, 31, 35 Block Diagram ............................................................ 35 RE0/RD/AN5 Pin .............................................. 9, 34, 35 RE1/WR/AN6 Pin ............................................. 9, 34, 35 RE2/CS/AN7 Pin .............................................. 9, 34, 35 Read Waveforms ........................................................ 36 Read/Write Enable (PSPIE Bit) .................................. 18 Read/Write Flag (PSPIF Bit)....................................... 19 Select (PSPMODE Bit) ................................... 31, 33, 35 Timing Diagram ........................................................ 113 Write Waveforms ........................................................ 35 PCON Register ............................................................. 22, 86 BOR Bit....................................................................... 22 POR Bit....................................................................... 22 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 98 PICDEM-2 Low-Cost PIC16CXX Demo Board................... 98 PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 98 PICMASTER(R) In-Circuit Emulator ..................................... 97 PICSTART(R) Plus Entry Level Development System ......... 97 PIE1 Register................................................................ 14, 18 ADIE Bit ...................................................................... 18 CCP1IE Bit ................................................................. 18 PSPIE Bit .................................................................... 18 RCIE Bit ...................................................................... 18 SSPIE Bit .................................................................... 18 TMR1IE Bit ................................................................. 18 TMR2IE Bit ................................................................. 18 TXIE Bit ...................................................................... 18 PIE2 Register................................................................ 14, 20 CCP2IE Bit ................................................................. 20 Pinout Descriptions PIC16C63A/PIC16C73B............................................... 7 PIC16C65B/PIC16C74B............................................... 8 PIR1 Register ............................................................... 13, 19 ADIF Bit ...................................................................... 19 CCP1IF Bit.................................................................. 19 PSPIF Bit .................................................................... 19
K
KeeLoq(R) Evaluation and Programming Tools.................... 99
M
Master Clear (MCLR) ........................................................ 7, 8 MCLR Reset, Normal Operation ..................... 83, 86, 87 MCLR Reset, SLEEP...................................... 83, 86, 87
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RCIF Bit ...................................................................... 19 SSPIF Bit .................................................................... 19 TMR1IF Bit.................................................................. 19 TMR2IF Bit.................................................................. 19 TXIF Bit ....................................................................... 19 PIR2 Register................................................................ 13, 21 CCP2IF Bit .................................................................. 21 Pointer, FSR ....................................................................... 24 PORTA.............................................................................. 7, 8 Analog Port Pins ....................................................... 7, 8 Initialization ................................................................. 25 PORTA Register ................................................... 13, 25 RA3:RA0 and RA5 Port Pins ...................................... 25 RA4/T0CKI Pin.................................................... 7, 8, 25 RA5/SS/AN4 Pin ................................................. 7, 8, 54 TRISA Register ..................................................... 14, 25 PORTB.............................................................................. 7, 8 Initialization ................................................................. 27 PORTB Register ................................................... 13, 27 Pull-up Enable (RBPU Bit) .......................................... 16 RB0/INT Edge Select (INTEDG Bit)............................ 16 RB0/INT Pin, External......................................... 7, 8, 91 RB3:RB0 Port Pins ..................................................... 27 RB7:RB4 Interrupt on Change .................................... 91 RB7:RB4 Interrupt on Change Enable (RBIE Bit) .............................................................. 17, 91 RB7:RB4 Interrupt on Change Flag (RBIF Bit) ........................................................ 17, 27, 91 RB7:RB4 Port Pins ..................................................... 27 TRISB Register ..................................................... 14, 27 PORTC ............................................................................. 7, 9 Block Diagram............................................................. 29 Initialization ................................................................. 29 PORTC Register ................................................... 13, 29 RC0/T1OSO/T1CKI Pin ............................................ 7, 9 RC1/T1OSI/CCP2 Pin............................................... 7, 9 RC2/CCP1 Pin .......................................................... 7, 9 RC3/SCK/SCL Pin ........................................ 7, 9, 54, 59 RC4/SDI/SDA Pin ............................................... 7, 9, 54 RC5/SDO Pin...................................................... 7, 9, 54 RC6/TX/CK Pin ................................................... 7, 9, 62 RC7/RX/DT Pin............................................. 7, 9, 62, 63 TRISC Register............................................... 14, 29, 61 PORTD ........................................................................... 9, 35 Block Diagram............................................................. 31 Parallel Slave Port (PSP) Function ............................. 31 PORTD Register ................................................... 13, 31 TRISD Register..................................................... 14, 31 PORTE.................................................................................. 9 Analog Port Pins ............................................... 9, 34, 35 Block Diagram............................................................. 33 Input Buffer Full Status (IBF Bit) ................................. 33 Input Buffer Overflow (IBOV Bit) ................................. 33 Output Buffer Full Status (OBF Bit)............................. 33 PORTE Register ................................................... 13, 33 PSP Mode Select (PSPMODE Bit) ................. 31, 33, 35 RE0/RD/AN5 Pin............................................... 9, 34, 35 RE1/WR/AN6 Pin.............................................. 9, 34, 35 RE2/CS/AN7 Pin............................................... 9, 34, 35 TRISE Register ..................................................... 14, 33 Postscaler, Timer2 Select (TOUTPS3:TOUTPS0 Bits) ............................. 43 Postscaler, WDT ................................................................. 37 Assignment (PSA Bit) ........................................... 16, 37 Block Diagram............................................................. 38 Rate Select (PS2:PS0 Bits) .................................. 16, 37 Switching Between Timer0 and WDT ......................... 38 Power-on Reset (POR)............................... 81, 83, 85, 86, 87 Oscillator Start-up Timer (OST)............................ 81, 85 POR Status (POR Bit) ................................................ 22 Power Control (PCON) Register................................. 86 Power-down (PD Bit) ............................................ 15, 83 Power-on Reset Circuit, External ............................... 85 Power-up Timer (PWRT) ...................................... 81, 85 PWRT Enable (PWRTE Bit) ....................................... 81 Time-out (TO Bit).................................................. 15, 83 Time-out Sequence .................................................... 86 Time-out Sequence on Power-up......................... 88, 89 Timing Diagram ........................................................ 110 Prescaler, Capture.............................................................. 46 Prescaler, Timer0 ............................................................... 37 Assignment (PSA Bit) ........................................... 16, 37 Block Diagram ............................................................ 38 Rate Select (PS2:PS0 Bits) .................................. 16, 37 Switching Between Timer0 and WDT......................... 38 Prescaler, Timer1 ............................................................... 40 Select (T1CKPS1:T1CKPS0 Bits) .............................. 39 Prescaler, Timer2 ............................................................... 48 Select (T2CKPS1:T2CKPS0 Bits) .............................. 43 PRO MATE(R) II Universal Programmer .............................. 97 Product Identification System ........................................... 149 Program Counter PCL Register ........................................................ 13, 23 PCLATH Register ........................................... 13, 23, 91 Reset Conditions ........................................................ 86 Program Memory ................................................................ 11 Interrupt Vector........................................................... 11 Paging .................................................................. 11, 23 Program Memory Map................................................ 11 Reset Vector............................................................... 11 Program Verification ........................................................... 94 Programming Pin (VPP) .................................................... 7, 8 Programming, Device Instructions...................................... 95 PWM (CCP Module) ........................................................... 48 Block Diagram ............................................................ 48 CCPR1H:CCPR1L Registers ..................................... 48 Duty Cycle .................................................................. 48 Example Frequencies/Resolutions ............................. 49 Output Diagram .......................................................... 48 Period ......................................................................... 48 Set-Up for PWM Operation......................................... 49 TMR2 to PR2 Match ............................................. 43, 48 TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 18 TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 19
Q
Q-Clock............................................................................... 48
R
RCSTA Register ................................................................. 62 CREN Bit .................................................................... 62 FERR Bit..................................................................... 62 OERR Bit .................................................................... 62 RX9 Bit ....................................................................... 62 RX9D Bit..................................................................... 62 SPEN Bit............................................................... 61, 62 SREN Bit .................................................................... 62 Reader Response............................................................. 148 Register File ....................................................................... 11 Register File Map ............................................................... 12 Reset ............................................................................ 81, 83 Block Diagram ............................................................ 84 Reset Conditions for All Registers.............................. 87 Reset Conditions for PCON Register ......................... 86 Reset Conditions for Program Counter ...................... 86 Reset Conditions for STATUS Register ..................... 86
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Timing Diagram......................................................... 110 Revision History ................................................................ 137
S
SEEVAL(R) Evaluation and Programming System ............... 99 SLEEP..................................................................... 81, 83, 93 Software Simulator (MPLAB-SIM)....................................... 99 Special Features of the CPU............................................... 81 Special Function Registers ........................................... 12, 13 Speed, Operating .......................................................... 1, 101 SPI (SSP Module) Block Diagram............................................................. 54 Buffer Full Status (BF Bit) ........................................... 52 Clock Edge Select (CKE Bit)....................................... 52 Clock Polarity Select (CKP Bit) ................................... 53 Data Input Sample Phase (SMP Bit)........................... 52 Mode Select (SSPM3:SSPM0 Bits) ............................ 53 Receive Overflow Indicator (SSPOV Bit) .................... 53 Serial Clock (RC3/SCK/SCL)...................................... 54 Serial Data In (RC4/SDI/SDA) .................................... 54 Serial Data Out (RC5/SDO) ........................................ 54 Slave Select (RA5/SS/AN4)........................................ 54 Synchronous Serial Port Enable (SSPEN Bit) ............ 53 SSP ..................................................................................... 51 Enable (SSPIE Bit)...................................................... 18 Flag (SSPIF Bit) .......................................................... 19 RA5/SS/AN4 Pin ....................................................... 7, 8 RC3/SCK/SCL Pin .................................................... 7, 9 RC4/SDI/SDA Pin ..................................................... 7, 9 RC5/SDO Pin............................................................ 7, 9 RCSTA Register ......................................................... 13 SPBRG Register ......................................................... 14 SSPADD Register....................................................... 14 SSPBUF Register ....................................................... 13 SSPCON Register ................................................ 13, 53 SSPSTAT Register ............................................... 14, 52 TMR2 Output for Clock Shift ................................. 43, 44 TXSTA Register .......................................................... 14 Write Collision Detect (WCOL Bit) .............................. 53 SSPCON Register............................................................... 53 CKP Bit ....................................................................... 53 SSPEN Bit................................................................... 53 SSPM3:SSPM0 Bits.................................................... 53 SSPOV Bit .................................................................. 53 WCOL Bit .................................................................... 53 SSPSTAT Register ............................................................. 52 BF Bit .......................................................................... 52 CKE Bit ....................................................................... 52 D/A Bit......................................................................... 52 P bit....................................................................... 52, 60 R/W Bit ...................................................... 52, 57, 58, 59 S Bit ...................................................................... 52, 60 SMP Bit ....................................................................... 52 UA Bit.......................................................................... 52 Stack ................................................................................... 23 STATUS Register.................................................... 13, 15, 91 C Bit ............................................................................ 15 DC Bit.......................................................................... 15 IRP Bit......................................................................... 15 PD Bit.................................................................... 15, 83 RP1:RP0 Bits .............................................................. 15 TO Bit .................................................................... 15, 83 Z Bit............................................................................. 15
T
T1CON Register............................................................ 13, 39 T1CKPS1:T1CKPS0 Bits ............................................ 39 T1OSCEN Bit.............................................................. 39 T1SYNC Bit................................................................. 39
TMR1CS Bit................................................................ 39 TMR1ON Bit ............................................................... 39 T2CON Register ........................................................... 13, 43 T2CKPS1:T2CKPS0 Bits............................................ 43 TMR2ON Bit ............................................................... 43 TOUTPS3:TOUTPS0 Bits .......................................... 43 Timer0................................................................................. 37 Block Diagram ............................................................ 37 Clock Source Edge Select (T0SE Bit) .................. 16, 37 Clock Source Select (T0CS Bit) ........................... 16, 37 Overflow Enable (T0IE Bit) ......................................... 17 Overflow Flag (T0IF Bit) ....................................... 17, 91 Overflow Interrupt ................................................. 38, 91 RA4/T0CKI Pin, External Clock ................................ 7, 8 Timing Diagram ........................................................ 111 TMR0 Register ........................................................... 13 Timer1................................................................................. 39 Block Diagram ............................................................ 40 Capacitor Selection .................................................... 41 Clock Source Select (TMR1CS Bit) ............................ 39 External Clock Input Sync (T1SYNC Bit).................... 39 Module On/Off (TMR1ON Bit) .................................... 39 Oscillator............................................................... 39, 41 Oscillator Enable (T1OSCEN Bit) ............................... 39 Overflow Enable (TMR1IE Bit) ................................... 18 Overflow Flag (TMR1IF Bit) ........................................ 19 Overflow Interrupt ................................................. 39, 41 RC0/T1OSO/T1CKI Pin ............................................ 7, 9 RC1/T1OSI/CCP2 Pin .............................................. 7, 9 Special Event Trigger (CCP) ................................ 41, 47 T1CON Register ................................................... 13, 39 Timing Diagram ........................................................ 111 TMR1H Register ................................................... 13, 39 TMR1L Register ................................................... 13, 39 Timer2 Block Diagram ............................................................ 44 PR2 Register .................................................. 14, 43, 48 SSP Clock Shift .................................................... 43, 44 T2CON Register ................................................... 13, 43 TMR2 Register ..................................................... 13, 43 TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 18 TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 19 TMR2 to PR2 Match Interrupt......................... 43, 44, 48 Timing Diagrams I2C Reception (7-bit Address)..................................... 58 Time-out Sequence on Power-up ......................... 88, 89 USART Asynchronous Master Transmission ............. 67 USART Asynchronous Reception .............................. 68 USART Synchronous Reception ................................ 72 USART Synchronous Transmission ........................... 71 Wake-up from SLEEP via Interrupt ............................ 94 Timing Diagrams and Specifications ................................ 108 A/D Conversion ........................................................ 122 Brown-out Reset (BOR)............................................ 110 Capture/Compare/PWM (CCP) ................................ 112 CLKOUT and I/O ...................................................... 109 External Clock .......................................................... 108 I2C Bus Data............................................................. 119 I2C Bus Start/Stop Bits ............................................. 118 Oscillator Start-up Timer (OST) ................................ 110 Parallel Slave Port (PSP) ......................................... 113 Power-up Timer (PWRT) .......................................... 110 Reset ........................................................................ 110 Timer0 and Timer1 ................................................... 111 USART Synchronous Receive ( Master/Slave) ......................................................... 120 USART SynchronousTransmission
DS30605A-page 144
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
( Master/Slave).......................................................... 120 Watchdog Timer (WDT) ............................................ 110 TRISE Register ............................................................. 14, 33 IBF Bit ......................................................................... 33 IBOV Bit ...................................................................... 33 OBF Bit ....................................................................... 33 PSPMODE Bit................................................. 31, 33, 35 TXSTA Register .................................................................. 61 BRGH Bit .............................................................. 61, 63 CSRC Bit..................................................................... 61 SYNC Bit..................................................................... 61 TRMT Bit..................................................................... 61 TX9 Bit ........................................................................ 61 TX9D Bit...................................................................... 61 TXEN Bit ..................................................................... 61 Timing Diagram .......................................................... 94 WDT Reset ................................................................. 87 Watchdog Timer (WDT)................................................ 81, 92 Block Diagram ............................................................ 92 Enable (WDTE Bit) ............................................... 81, 92 Programming Considerations ..................................... 92 RC Oscillator .............................................................. 92 Time-out Period .......................................................... 92 Timing Diagram ........................................................ 110 WDT Reset, Normal Operation....................... 83, 86, 87 WDT Reset, SLEEP ....................................... 83, 86, 87 WWW, On-Line Support ............................................... 4, 147
U
USART ................................................................................ 61 Asynchronous Mode ................................................... 66 Master Transmission .......................................... 67 Receive Block Diagram ...................................... 68 Reception............................................................ 68 Transmit Block Diagram ..................................... 66 Baud Rate Generator (BRG)....................................... 63 Baud Rate Error, Calculating .............................. 63 Baud Rate Formula............................................. 63 Baud Rates, Asynchronous Mode (BRGH=0) ........................................................... 64 Baud Rates, Asynchronous Mode (BRGH=1) ........................................................... 65 Baud Rates, Synchronous Mode ........................ 64 High Baud Rate Select (BRGH Bit) .............. 61, 63 Sampling............................................................. 63 Clock Source Select (CSRC Bit)................................. 61 Continuous Receive Enable (CREN Bit)..................... 62 Framing Error (FERR Bit) ........................................... 62 Mode Select (SYNC Bit) ............................................. 61 Overrun Error (OERR Bit) ........................................... 62 RC6/TX/CK Pin ......................................................... 7, 9 RC7/RX/DT Pin......................................................... 7, 9 RCREG Register......................................................... 13 RCSTA Register ......................................................... 62 Receive Data, 9th bit (RX9D Bit) ................................ 62 Receive Enable (RCIE Bit).......................................... 18 Receive Enable, 9-bit (RX9 Bit) .................................. 62 Receive Flag (RCIF Bit) .............................................. 19 Serial Port Enable (SPEN Bit)............................... 61, 62 Single Receive Enable (SREN Bit) ............................. 62 Synchronous Master Mode ......................................... 70 Reception............................................................ 72 Timing Diagram, Synchronous Receive ........... 120 Timing Diagram, Synchronous Transmission .................................................... 120 Transmission ...................................................... 71 Synchronous Slave Mode ........................................... 73 Transmit Data, 9th Bit (TX9D)..................................... 61 Transmit Enable (TXEN Bit)........................................ 61 Transmit Enable (TXIE Bit) ......................................... 18 Transmit Enable, Nine-bit (TX9 Bit) ............................ 61 Transmit Flag (TXIE Bit) ............................................. 19 Transmit Shift Register Status (TRMT Bit).................. 61 TXREG Register ......................................................... 13 TXSTA Register .......................................................... 61
W
W Register .......................................................................... 91 Wake-up from SLEEP................................................... 81, 93 Interrupts............................................................... 86, 87 MCLR Reset ............................................................... 87
(c) 1998 Microchip Technology Inc.
DS30605A-page 145
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 146
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
980106
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies.
(c) 1998 Microchip Technology Inc.
DS30605A-page 147
PIC16C63A/65B/73B/74B
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N FAX: (______) _________ - _________
Device: PIC16C63A/65B/73B/74B Literature Number: DS30605A Questions: 1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30605A-page 148
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
PIC16C63A/65B/73B/74B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -XX X /XX Package XXX Pattern Examples: a)
b) Device PIC16C6X(1), PIC16C6XT(2);VDD range 4.0V to PIC16LC6X(1), PIC16LC6XT(2);VDD range 2.5V PIC16C7X(1), PIC16C7XT(2);VDD range 4.0V to (1) (2) 5.5V to 5.5V 5.5V PIC16LC7X , PIC16LC7XT ;VDD range 2.5V to 5.5V c) PIC16C74B -04/P 301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. PIC16LC63A - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. PIC16C65B - 20I/P = Industrial temp., PDIP package, 20MHz, normal VDD limits.
Frequency Temperature Range Range
Frequency Range
04 20
= 4 MHz = 20 MHz
Note 1: 2:
C LC T
Temperature Range
blank I E
= 0C to 70C = -40C to +85C = -40C to +125C
(Commercial) (Industrial) (Extended)
= CMOS = Low Power CMOS = in tape and reel - SOIC, SSOP, PLCC, QFP, TQ and FP packages only.
Package
JW PQ PT SO SP P L SS
= = = = = = = =
Windowed CERDIP MQFP (Metric PQFP) TQFP (Thin Quad Flatpack) SOIC Skinny plastic dip PDIP PLCC SSOP
Pattern
QTP, SQTP, Code or Special Requirements (blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices).
(c) 1998 Microchip Technology Inc.
DS30605A-page 149
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 150
(c) 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
NOTES:
(c) 1998 Microchip Technology Inc.
DS30605A-page 151
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com
AMERICAS (continued)
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Dallas
Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Detroit
Microchip Technology Inc. 42705 Grand River, Suite 201 Novi, MI 48375-1727 Tel: 248-374-1888 Fax: 248-374-2874
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 7/7/98
Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 1998, Microchip Technology Incorporated, USA. 8/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30605A-page 152
(c) 1998 Microchip Technology Inc.

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